e49679d5a1
With this patch, output on usbdebug also includes the section of MTRR setups for every CPU. This makes usbdebug output almost identical with that of serial port and CBMEM console. Tested with model_206ax. Also tested previously on model_f2x which does not have these disable/enable calls in model_f2x_init() without detected issues. Change-Id: Idfd0e93439907b17255633658195d698feab3895 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3423 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
562 lines
14 KiB
C
562 lines
14 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/intel/speedstep.h>
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#include <cpu/intel/turbo.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/name.h>
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#include <pc80/mc146818rtc.h>
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#include <usbdebug.h>
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#include "haswell.h"
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#include "chip.h"
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/*
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* List of suported C-states in this processor
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*
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* Latencies are typical worst-case package exit time in uS
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* taken from the SandyBridge BIOS specification.
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*/
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#if 0
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static acpi_cstate_t cstate_map[] = {
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{ /* 0: C0 */
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},{ /* 1: C1 */
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.latency = 1,
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.power = 1000,
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.resource = {
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.addrl = 0x00, /* MWAIT State 0 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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{ /* 2: C1E */
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.latency = 1,
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.power = 1000,
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.resource = {
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.addrl = 0x01, /* MWAIT State 0 Sub-state 1 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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{ /* 3: C3 */
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.latency = 63,
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.power = 500,
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.resource = {
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.addrl = 0x10, /* MWAIT State 1 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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{ /* 4: C6 */
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.latency = 87,
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.power = 350,
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.resource = {
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.addrl = 0x20, /* MWAIT State 2 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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{ /* 5: C7 */
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.latency = 90,
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.power = 200,
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.resource = {
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.addrl = 0x30, /* MWAIT State 3 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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{ /* 6: C7S */
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.latency = 90,
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.power = 200,
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.resource = {
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.addrl = 0x31, /* MWAIT State 3 Sub-state 1 */
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.space_id = ACPI_ADDRESS_SPACE_FIXED,
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
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}
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},
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{ 0 }
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};
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#endif
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/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
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static const u8 power_limit_time_sec_to_msr[] = {
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[0] = 0x00,
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[1] = 0x0a,
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[2] = 0x0b,
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[3] = 0x4b,
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[4] = 0x0c,
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[5] = 0x2c,
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[6] = 0x4c,
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[7] = 0x6c,
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[8] = 0x0d,
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[10] = 0x2d,
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[12] = 0x4d,
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[14] = 0x6d,
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[16] = 0x0e,
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[20] = 0x2e,
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[24] = 0x4e,
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[28] = 0x6e,
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[32] = 0x0f,
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[40] = 0x2f,
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[48] = 0x4f,
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[56] = 0x6f,
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[64] = 0x10,
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[80] = 0x30,
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[96] = 0x50,
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[112] = 0x70,
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[128] = 0x11,
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};
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/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
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static const u8 power_limit_time_msr_to_sec[] = {
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[0x00] = 0,
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[0x0a] = 1,
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[0x0b] = 2,
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[0x4b] = 3,
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[0x0c] = 4,
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[0x2c] = 5,
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[0x4c] = 6,
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[0x6c] = 7,
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[0x0d] = 8,
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[0x2d] = 10,
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[0x4d] = 12,
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[0x6d] = 14,
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[0x0e] = 16,
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[0x2e] = 20,
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[0x4e] = 24,
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[0x6e] = 28,
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[0x0f] = 32,
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[0x2f] = 40,
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[0x4f] = 48,
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[0x6f] = 56,
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[0x10] = 64,
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[0x30] = 80,
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[0x50] = 96,
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[0x70] = 112,
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[0x11] = 128,
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};
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int cpu_config_tdp_levels(void)
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{
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msr_t platform_info;
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/* Bits 34:33 indicate how many levels supported */
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platform_info = rdmsr(MSR_PLATFORM_INFO);
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return (platform_info.hi >> 1) & 3;
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}
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/*
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* Configure processor power limits if possible
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* This must be done AFTER set of BIOS_RESET_CPL
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*/
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void set_power_limits(u8 power_limit_1_time)
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{
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msr_t msr = rdmsr(MSR_PLATFORM_INFO);
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msr_t limit;
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unsigned power_unit;
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unsigned tdp, min_power, max_power, max_time;
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u8 power_limit_1_val;
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if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
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return;
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if (!(msr.lo & PLATFORM_INFO_SET_TDP))
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return;
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/* Get units */
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msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
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power_unit = 2 << ((msr.lo & 0xf) - 1);
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/* Get power defaults for this SKU */
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msr = rdmsr(MSR_PKG_POWER_SKU);
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tdp = msr.lo & 0x7fff;
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min_power = (msr.lo >> 16) & 0x7fff;
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max_power = msr.hi & 0x7fff;
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max_time = (msr.hi >> 16) & 0x7f;
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printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
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if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
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power_limit_1_time = power_limit_time_msr_to_sec[max_time];
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if (min_power > 0 && tdp < min_power)
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tdp = min_power;
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if (max_power > 0 && tdp > max_power)
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tdp = max_power;
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power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
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/* Set long term power limit to TDP */
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limit.lo = 0;
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limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
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limit.lo |= PKG_POWER_LIMIT_EN;
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limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
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PKG_POWER_LIMIT_TIME_SHIFT;
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/* Set short term power limit to 1.25 * TDP */
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limit.hi = 0;
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limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
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limit.hi |= PKG_POWER_LIMIT_EN;
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/* Power limit 2 time is only programmable on SNB EP/EX */
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wrmsr(MSR_PKG_POWER_LIMIT, limit);
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/* Use nominal TDP values for CPUs with configurable TDP */
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if (cpu_config_tdp_levels()) {
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msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
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limit.hi = 0;
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limit.lo = msr.lo & 0xff;
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wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
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}
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}
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#if 0
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static void configure_c_states(void)
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{
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msr_t msr;
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msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
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msr.lo |= (1 << 28); // C1 Auto Undemotion Enable
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msr.lo |= (1 << 27); // C3 Auto Undemotion Enable
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msr.lo |= (1 << 26); // C1 Auto Demotion Enable
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msr.lo |= (1 << 25); // C3 Auto Demotion Enable
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msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
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msr.lo |= 7; // No package C-state limit
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wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
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msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
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msr.lo &= ~0x7ffff;
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msr.lo |= (get_pmbase() + 4); // LVL_2 base address
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msr.lo |= (2 << 16); // CST Range: C7 is max C-state
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wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
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msr = rdmsr(MSR_MISC_PWR_MGMT);
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msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination
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wrmsr(MSR_MISC_PWR_MGMT, msr);
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msr = rdmsr(MSR_POWER_CTL);
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msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0
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msr.lo |= (1 << 1); // C1E Enable
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msr.lo |= (1 << 0); // Bi-directional PROCHOT#
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wrmsr(MSR_POWER_CTL, msr);
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/* C3 Interrupt Response Time Limit */
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
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wrmsr(MSR_PKGC3_IRTL, msr);
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/* C6 Interrupt Response Time Limit */
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
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wrmsr(MSR_PKGC6_IRTL, msr);
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/* C7 Interrupt Response Time Limit */
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
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wrmsr(MSR_PKGC7_IRTL, msr);
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/* Primary Plane Current Limit */
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msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
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msr.lo &= ~0x1fff;
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msr.lo |= PP0_CURRENT_LIMIT;
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wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
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/* Secondary Plane Current Limit */
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msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
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msr.lo &= ~0x1fff;
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if (cpuid_eax(1) >= 0x30600)
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msr.lo |= PP1_CURRENT_LIMIT_IVB;
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else
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msr.lo |= PP1_CURRENT_LIMIT_SNB;
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wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
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}
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#endif
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static void configure_thermal_target(void)
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{
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struct cpu_intel_haswell_config *conf;
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device_t lapic;
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msr_t msr;
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/* Find pointer to CPU configuration */
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lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
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if (!lapic || !lapic->chip_info)
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return;
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conf = lapic->chip_info;
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/* Set TCC activaiton offset if supported */
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msr = rdmsr(MSR_PLATFORM_INFO);
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if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
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msr = rdmsr(MSR_TEMPERATURE_TARGET);
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msr.lo &= ~(0xf << 24); /* Bits 27:24 */
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msr.lo |= (conf->tcc_offset & 0xf) << 24;
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wrmsr(MSR_TEMPERATURE_TARGET, msr);
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}
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}
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static void configure_misc(void)
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{
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msr_t msr;
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 0); /* Fast String enable */
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msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
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msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
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wrmsr(IA32_MISC_ENABLE, msr);
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/* Disable Thermal interrupts */
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msr.lo = 0;
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msr.hi = 0;
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wrmsr(IA32_THERM_INTERRUPT, msr);
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/* Enable package critical interrupt only */
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msr.lo = 1 << 4;
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msr.hi = 0;
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wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
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}
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static void enable_lapic_tpr(void)
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{
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msr_t msr;
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msr = rdmsr(MSR_PIC_MSG_CONTROL);
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msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
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wrmsr(MSR_PIC_MSG_CONTROL, msr);
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}
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static void configure_dca_cap(void)
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{
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struct cpuid_result cpuid_regs;
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msr_t msr;
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/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
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cpuid_regs = cpuid(1);
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if (cpuid_regs.ecx & (1 << 18)) {
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msr = rdmsr(IA32_PLATFORM_DCA_CAP);
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msr.lo |= 1;
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wrmsr(IA32_PLATFORM_DCA_CAP, msr);
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}
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}
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static void set_max_ratio(void)
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{
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msr_t msr, perf_ctl;
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perf_ctl.hi = 0;
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/* Check for configurable TDP option */
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if (cpu_config_tdp_levels()) {
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/* Set to nominal TDP ratio */
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msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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} else {
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/* Platform Info bits 15:8 give max ratio */
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msr = rdmsr(MSR_PLATFORM_INFO);
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perf_ctl.lo = msr.lo & 0xff00;
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}
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wrmsr(IA32_PERF_CTL, perf_ctl);
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printk(BIOS_DEBUG, "haswell: frequency set to %d\n",
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((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK);
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}
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static void set_energy_perf_bias(u8 policy)
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{
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msr_t msr;
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int ecx;
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/* Determine if energy efficient policy is supported. */
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ecx = cpuid_ecx(0x6);
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if (!(ecx & (1 << 3)))
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return;
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/* Energy Policy is bits 3:0 */
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msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
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msr.lo &= ~0xf;
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msr.lo |= policy & 0xf;
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wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
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printk(BIOS_DEBUG, "haswell: energy policy set to %u\n",
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policy);
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}
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static void configure_mca(void)
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{
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msr_t msr;
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const unsigned int mcg_cap_msr = 0x179;
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int i;
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int num_banks;
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msr = rdmsr(mcg_cap_msr);
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num_banks = msr.lo & 0xff;
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msr.lo = msr.hi = 0;
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/* TODO(adurbin): This should only be done on a cold boot. Also, some
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* of these banks are core vs package scope. For now every CPU clears
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* every bank. */
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for (i = 0; i < num_banks; i++)
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wrmsr(IA32_MC0_STATUS + (i * 4), msr);
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}
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static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
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{
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struct device_path cpu_path;
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struct cpu_info *info;
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char processor_name[49];
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/* Print processor name */
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fill_processor_name(processor_name);
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printk(BIOS_INFO, "CPU: %s.\n", processor_name);
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/* Ensure the local apic is enabled */
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enable_lapic();
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/* Set the device path of the boot cpu. */
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cpu_path.type = DEVICE_PATH_APIC;
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cpu_path.apic.apic_id = lapicid();
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/* Find the device structure for the boot cpu. */
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info = cpu_info();
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info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
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if (info->index != 0)
|
|
printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index);
|
|
|
|
/* Setup MTRRs based on physical address size. */
|
|
x86_setup_fixed_mtrrs();
|
|
x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
|
|
x86_mtrr_check();
|
|
|
|
/* Call through the cpu driver's initialization. */
|
|
cpu_initialize(0);
|
|
}
|
|
|
|
/* All CPUs including BSP will run the following function. */
|
|
static void haswell_init(device_t cpu)
|
|
{
|
|
/* Clear out pending MCEs */
|
|
configure_mca();
|
|
|
|
/* Enable the local cpu apics */
|
|
enable_lapic_tpr();
|
|
setup_lapic();
|
|
|
|
/* Configure C States */
|
|
//configure_c_states();
|
|
|
|
/* Configure Enhanced SpeedStep and Thermal Sensors */
|
|
configure_misc();
|
|
|
|
/* Thermal throttle activation offset */
|
|
configure_thermal_target();
|
|
|
|
/* Enable Direct Cache Access */
|
|
configure_dca_cap();
|
|
|
|
/* Set energy policy */
|
|
set_energy_perf_bias(ENERGY_POLICY_NORMAL);
|
|
|
|
/* Set Max Ratio */
|
|
set_max_ratio();
|
|
|
|
/* Enable Turbo */
|
|
enable_turbo();
|
|
}
|
|
|
|
void bsp_init_and_start_aps(struct bus *cpu_bus)
|
|
{
|
|
int max_cpus;
|
|
int num_aps;
|
|
const void *microcode_patch;
|
|
|
|
/* Perform any necesarry BSP initialization before APs are brought up.
|
|
* This call alos allows the BSP to prepare for any secondary effects
|
|
* from calling cpu_initialize() such as smm_init(). */
|
|
bsp_init_before_ap_bringup(cpu_bus);
|
|
|
|
microcode_patch = intel_microcode_find();
|
|
|
|
/* This needs to be called after the mtrr setup so the BSP mtrrs
|
|
* can be mirrored by the APs. */
|
|
if (setup_ap_init(cpu_bus, &max_cpus, microcode_patch)) {
|
|
printk(BIOS_CRIT, "AP setup initialization failed. "
|
|
"No APs will be brought up.\n");
|
|
return;
|
|
}
|
|
|
|
num_aps = max_cpus - 1;
|
|
if (start_aps(cpu_bus, num_aps)) {
|
|
printk(BIOS_CRIT, "AP startup failed. Trying to continue.\n");
|
|
}
|
|
|
|
if (smm_initialize()) {
|
|
printk(BIOS_CRIT, "SMM Initialiazation failed...\n");
|
|
return;
|
|
}
|
|
|
|
/* After SMM relocation a 2nd microcode load is required. */
|
|
intel_microcode_load_unlocked(microcode_patch);
|
|
|
|
/* Enable ROM caching if option was selected. */
|
|
x86_mtrr_enable_rom_caching();
|
|
}
|
|
|
|
static struct device_operations cpu_dev_ops = {
|
|
.init = haswell_init,
|
|
};
|
|
|
|
static struct cpu_device_id cpu_table[] = {
|
|
{ X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */
|
|
{ X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */
|
|
{ X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */
|
|
{ X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */
|
|
{ 0, 0 },
|
|
};
|
|
|
|
static const struct cpu_driver driver __cpu_driver = {
|
|
.ops = &cpu_dev_ops,
|
|
.id_table = cpu_table,
|
|
/* .cstates = cstate_map, */
|
|
};
|
|
|