e50bb8fc9e
Motivation is to have mainboard_chromeos_acpi_generate() do nothing else than fill ACPI \OIPG package. Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
117 lines
2.6 KiB
C
117 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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#include <bootmode.h>
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#include <types.h>
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#include <string.h>
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#include <stdlib.h>
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#include <cbfs.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <ec/google/chromeec/ec.h>
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#include <fmap.h>
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#include <security/vboot/vbnv.h>
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#include <security/vboot/vboot_common.h>
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#include <smbios.h>
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#include "chromeos.h"
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#include "gnvs.h"
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static struct chromeos_acpi *chromeos_acpi;
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static size_t chromeos_vpd_region(const char *region, uintptr_t *base)
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{
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struct region_device vpd;
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if (fmap_locate_area_as_rdev(region, &vpd))
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return 0;
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*base = (uintptr_t)rdev_mmap_full(&vpd);
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return region_device_sz(&vpd);
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}
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__weak bool mainboard_ec_running_ro(void) { return true; }
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void chromeos_init_chromeos_acpi(void)
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{
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size_t vpd_size;
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uintptr_t vpd_base = 0;
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chromeos_acpi = cbmem_add(CBMEM_ID_ACPI_CNVS, sizeof(struct chromeos_acpi));
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if (!chromeos_acpi)
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return;
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/* Retain CNVS contents on S3 resume path. */
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if (acpi_is_wakeup_s3())
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return;
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vpd_size = chromeos_vpd_region("RO_VPD", &vpd_base);
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if (vpd_size && vpd_base) {
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chromeos_acpi->vpd_ro_base = vpd_base;
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chromeos_acpi->vpd_ro_size = vpd_size;
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}
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vpd_size = chromeos_vpd_region("RW_VPD", &vpd_base);
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if (vpd_size && vpd_base) {
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chromeos_acpi->vpd_rw_base = vpd_base;
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chromeos_acpi->vpd_rw_size = vpd_size;
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}
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/* EC can override to ECFW_RW. */
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chromeos_acpi->vbt2 = ACTIVE_ECFW_RO;
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if (CONFIG(EC_GOOGLE_CHROMEEC)) {
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if (!google_ec_running_ro())
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chromeos_acpi->vbt2 = ACTIVE_ECFW_RW;
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} else {
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if (!mainboard_ec_running_ro())
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chromeos_acpi->vbt2 = ACTIVE_ECFW_RW;
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}
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}
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void chromeos_set_me_hash(u32 *hash, int len)
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{
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if ((len*sizeof(u32)) > sizeof(chromeos_acpi->mehh))
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return;
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/* Copy to NVS. */
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if (chromeos_acpi)
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memcpy(chromeos_acpi->mehh, hash, len*sizeof(u32));
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}
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void chromeos_set_ramoops(void *ram_oops, size_t size)
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{
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if (!chromeos_acpi)
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return;
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printk(BIOS_DEBUG, "Ramoops buffer: 0x%zx@%p.\n", size, ram_oops);
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chromeos_acpi->ramoops_base = (uintptr_t)ram_oops;
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chromeos_acpi->ramoops_len = size;
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}
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void smbios_type0_bios_version(uintptr_t address)
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{
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if (!chromeos_acpi)
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return;
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/* Location of smbios_type0.bios_version() string filled with spaces. */
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chromeos_acpi->vbt10 = address;
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}
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void acpi_fill_cnvs(void)
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{
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const struct opregion cnvs_op = OPREGION("CNVS", SYSTEMMEMORY, (uintptr_t)chromeos_acpi,
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sizeof(*chromeos_acpi));
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if (!chromeos_acpi)
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return;
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acpigen_write_scope("\\");
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acpigen_write_opregion(&cnvs_op);
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acpigen_pop_len();
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/* Usually this creates OIPG package for GPIOs. */
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mainboard_chromeos_acpi_generate();
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}
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