e55a7c5403
The entries in chip.h are used to set the UPD values. These had originally been shortened and did not match the names of the structure entries in vendorcode/intel/fsp/baytrail/include/fspvpd.h This patch aligns the names. - Update names in chip.h. - Update names in devictree registers for bayley bay and minnow max. - Update names in chipset_fsp_util.c Change-Id: I8d7e34195cec2e63802d7e07e5aed71735556936 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7486 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
82 lines
3.7 KiB
Plaintext
82 lines
3.7 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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chip soc/intel/fsp_baytrail
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#### ACPI Register Settings ####
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register "fadt_pm_profile" = "PM_MOBILE"
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
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#### FSP register settings ####
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register "PcdSataMode" = "SATA_MODE_AHCI"
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register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
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register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
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register "PcdMrcInitTsegSize" = "TSEG_SIZE_8_MB"
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register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
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register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
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register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
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register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
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register "PcdGttSize" = "GTT_SIZE_DEFAULT"
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register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
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register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
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register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # 8086 0F00 - SoC router
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device pci 02.0 on end # 8086 0F31 - GFX
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device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
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device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
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device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
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device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
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device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
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device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
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device pci 15.0 off end # 8086 0F28 - LP Engine Audio
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device pci 16.0 off end # 8086 0F37 - OTG controller
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device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
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device pci 18.0 on end # 8086 0F40 - SIO - DMA
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device pci 18.1 on end # 8086 0F41 - I2C Port 1
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device pci 18.2 on end # 8086 0F42 - I2C Port 2
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device pci 18.3 on end # 8086 0F43 - I2C Port 3
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device pci 18.4 on end # 8086 0F44 - I2C Port 4
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device pci 18.5 on end # 8086 0F45 - I2C Port 5
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device pci 18.6 on end # 8086 0F46 - I2C Port 6
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device pci 18.7 on end # 8086 0F47 - I2C Port 7
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device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
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device pci 1b.0 on end # 8086 0F04 - HD Audio
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device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (x4 slot)
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device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)
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device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot)
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device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot)
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device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
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device pci 1e.0 on end # 8086 0F06 - SIO - DMA
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device pci 1e.1 on end # 8086 0F08 - PWM 1
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device pci 1e.2 on end # 8086 0F09 - PWM 2
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device pci 1e.3 on end # 8086 0F0A - HSUART 1
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device pci 1e.4 on end # 8086 0F0C - HSUART 2
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device pci 1e.5 on end # 8086 0F0E - SPI
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device pci 1f.0 on end # 8086 0F1C - LPC bridge
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device pci 1f.3 on end # 8086 0F12 - SMBus 0
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end
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end
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