f6e74c45c0
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ie06cfa598f40a734994abb2bc2eb8f01f9331f7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
79 lines
2.5 KiB
C
79 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/acpimmio_legacy_gpio100.h>
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#include <device/device.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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static const u8 mainboard_intr_data[] = {
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[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
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[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
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[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00,
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[0x18] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
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[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
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[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x50] = 0x10, 0x11, 0x12, 0x13
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};
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static void init_gpios(void)
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{
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/**
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* GPIO32 Pcie Device DeAssert for APU
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* GPIO25 Pcie LAN, APU GPP2
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* GPIO02 MINIPCIE SLOT1, APU GPP3
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* GPIO50 Pcie Device DeAssert for Hudson Southbridge
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* GPIO05 Express Card, SB GPP0
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* GPIO26 NEC USB3.0GPPUSB, SB GPP1
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* GPIO00 MINIPCIE SLOT2, SB GPP2
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* GPIO05 Pcie X1 Slot, SB GPP3
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*/
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/* Multi-function pins switch to GPIO0-35, these pins are shared with
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* PCI pins, make sure Hudson PCI device is disabled.
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*/
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pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
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/* select IOMux to function1/2, corresponds to GPIO */
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iomux_write8(0x32, (iomux_read8(0x32) & 0xfc) | 1);
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iomux_write8(0x50, (iomux_read8(0x50) & 0xfc) | 2);
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/* output low */
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gpio_100_write8(0x20, 0x48);
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gpio_100_write8(0x32, 0x48);
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}
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/* PIRQ Setup */
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static void pirq_setup(void)
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{
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intr_data_ptr = mainboard_intr_data;
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}
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/**********************************************
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* Enable the dedicated functions of the board.
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**********************************************/
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static void mainboard_enable(struct device *dev)
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{
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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/* Inagua mainboard specific setting */
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init_gpios();
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/*
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* Initialize ASF registers to an arbitrary address because someone
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* long ago set things up this way inside the SPD read code. The
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* SPD read code has been made generic and moved out of the board
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* directory, so the ASF init is being done here.
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*/
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pm_write8(0x29, 0x80);
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pm_write8(0x28, 0x61);
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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