afa39105d8
This patch introduces x86_64 (64-bit) support to the payload, building upon the existing x86 (32-bit) architecture. Files necessary for 64-bit compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig option. BUG=b:242829490 TEST=Able to verify all valid combinations between coreboot and payload with this patch. Payload Entry Point Behavior with below code. +----------------+--------------------+----------------------------+ | LP_ARCH_X86_64 | Payload Entry Mode | Description | +----------------+--------------------+----------------------------+ | No | 32-bit | Direct protected mode init | +----------------+--------------------+----------------------------+ | Yes | 32-bit | Protected to long mode | +----------------+--------------------+----------------------------+ | Yes | 64-bit | Long mode initialization | +----------------+--------------------+----------------------------+ Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81968 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
/*
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARCH_EXCEPTION_H
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#define _ARCH_EXCEPTION_H
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#include <stddef.h>
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#include <stdint.h>
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void exception_init_asm(void);
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void exception_dispatch(void);
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void enable_interrupts(void);
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void disable_interrupts(void);
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/** Returns 1 if interrupts are enabled. */
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int interrupts_enabled(void);
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#if CONFIG(LP_ARCH_X86_64)
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struct exception_state {
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/* Careful: x86/gdb.c currently relies on the size and order of regs. */
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struct {
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size_t reg_ax;
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size_t reg_bx;
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size_t reg_cx;
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size_t reg_dx;
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size_t reg_si;
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size_t reg_di;
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size_t reg_bp;
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size_t reg_sp;
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size_t reg_r8;
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size_t reg_r9;
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size_t reg_r10;
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size_t reg_r11;
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size_t reg_r12;
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size_t reg_r13;
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size_t reg_r14;
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size_t reg_r15;
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size_t reg_ip;
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size_t reg_flags;
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u32 cs;
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u32 ss;
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u32 ds;
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u32 es;
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u32 fs;
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u32 gs;
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} regs;
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size_t error_code;
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size_t vector;
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} __packed;
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#else
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struct exception_state {
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/* Careful: x86/gdb.c currently relies on the size and order of regs. */
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struct {
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size_t reg_ax;
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size_t reg_cx;
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size_t reg_dx;
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size_t reg_bx;
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size_t reg_sp;
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size_t reg_bp;
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size_t reg_si;
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size_t reg_di;
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size_t reg_ip;
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size_t reg_flags;
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u32 cs;
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u32 ss;
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u32 ds;
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u32 es;
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u32 fs;
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u32 gs;
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} regs;
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size_t error_code;
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size_t vector;
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} __packed;
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#endif
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extern struct exception_state *exception_state;
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extern u8 exception_stack[];
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extern u8 *exception_stack_end;
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enum {
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EXC_DE = 0, /* Divide by zero */
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EXC_DB = 1, /* Debug */
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EXC_NMI = 2, /* Non maskable interrupt */
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EXC_BP = 3, /* Breakpoint */
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EXC_OF = 4, /* Overflow */
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EXC_BR = 5, /* Bound range */
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EXC_UD = 6, /* Invalid opcode */
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EXC_NM = 7, /* Device not available */
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EXC_DF = 8, /* Double fault */
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EXC_TS = 10, /* Invalid TSS */
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EXC_NP = 11, /* Segment not present */
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EXC_SS = 12, /* Stack */
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EXC_GP = 13, /* General protection */
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EXC_PF = 14, /* Page fault */
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EXC_MF = 16, /* x87 floating point */
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EXC_AC = 17, /* Alignment check */
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EXC_MC = 18, /* Machine check */
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EXC_XF = 19, /* SIMD floating point */
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EXC_SX = 30, /* Security */
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EXC_COUNT
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};
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#endif
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