e697fd9ecb
The SoC code has in implicit dependency on this option, so select it in the SoC code instead of the mainboard code. Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
150 lines
3.7 KiB
Plaintext
150 lines
3.7 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select SOC_AMD_COMMON_BLOCK_USE_ESPI
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select SOC_AMD_PICASSO
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select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN
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select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME
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select AZALIA_PLUGIN_SUPPORT
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select HAVE_ACPI_RESUME
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select DRIVERS_UART_ACPI
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select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD
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config FMDFILE
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string
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default "src/mainboard/amd/mandolin/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
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config AMD_LPC_DEBUG_CARD
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bool "Enable LPC-Serial debug card on the debug header"
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default n
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select MANDOLIN_LPC
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select SUPERIO_SMSC_SIO1036
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help
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AMD's debug card contains an SMSC SIO1036 device which provides an
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I/O-mapped UART in the system. This is mutually exclusive with
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AMD_SOC_CONSOLE_UART which selects the SoC's integrated memory-mapped
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UART for coreboot console output.
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choice
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prompt "SMSC/Microchip 1036 SuperIO config address"
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depends on SUPERIO_SMSC_SIO1036
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default SMSC_SIO1036_BASE_164E
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config SMSC_SIO1036_BASE_4E
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bool "0x4e/0x4d base address"
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config SMSC_SIO1036_BASE_164E
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bool "0x164e/0x164d base address"
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endchoice
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config SUPERIO_ADDR_BASE
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hex
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default 0x4e if SMSC_SIO1036_BASE_4E
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default 0x164e if SMSC_SIO1036_BASE_164E
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config CBFS_SIZE
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hex
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default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP
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default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP
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config MAINBOARD_DIR
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string
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default "amd/mandolin"
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config VARIANT_DIR
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string
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default "mandolin" if BOARD_AMD_MANDOLIN
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default "cereme" if BOARD_AMD_CEREME
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config MAINBOARD_PART_NUMBER
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string
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default "MANDOLIN" if BOARD_AMD_MANDOLIN
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default "CEREME" if BOARD_AMD_CEREME
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config DEVICETREE
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string
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config AMD_FWM_POSITION_INDEX
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int
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default 3 if BOARD_AMD_MANDOLIN
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default 4 if BOARD_AMD_CEREME
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help
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TODO: might need to be adapted for better placement of files in cbfs
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config MANDOLIN_HAVE_MCHP_FW
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bool "Have Microchip EC firmware?"
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default n
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config MANDOLIN_MCHP_FW_FILE
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string
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depends on MANDOLIN_HAVE_MCHP_FW
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default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN
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default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_CEREME
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help
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The EC firmware blob is usually the first 128kByte of the stock
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firmware image.
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if !AMD_LPC_DEBUG_CARD
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choice
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prompt "State of IOMux for LPC/eMMC signals"
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default MANDOLIN_IOMUX_USE_EMMC
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help
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Mandolin is designed to use either LPC or eMMC signals. Use this
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selection to determine which are configured for this image.
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config MANDOLIN_IOMUX_USE_LPC
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bool "LPC signals"
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config MANDOLIN_IOMUX_USE_EMMC
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bool "eMMC signals"
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endchoice
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endif # !AMD_LPC_DEBUG_CARD
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config MANDOLIN_LPC
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bool
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default y if MANDOLIN_IOMUX_USE_LPC
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help
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Picasso's LPC bus signals are MUXed with some of the EMMC signals.
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Select this option if LPC signals are required.
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#TODO: remove this hack to not break graphics in combination with SeaBIOS
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config VGA_BIOS_DGPU_ID
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string
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default "1002,15d8"
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help
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The default VGA BIOS PCI vendor/device ID should be set to the
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result of the map_oprom_vendev() function in northbridge.c.
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config VGA_BIOS_DGPU_FILE
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string
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default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN
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default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME
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config EFS_SPI_READ_MODE
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int
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default 0 if EM100
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default 0 if BOARD_AMD_CEREME
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default 3
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config EFS_SPI_SPEED
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int
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default 3 if EM100
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default 1 if BOARD_AMD_CEREME
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default 0
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config EFS_SPI_MICRON_FLAG
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int
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default 0
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endif # BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
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