Subrata Banik 447233ce8c soc/intel/alderlake: Update UART0 GPIO as per latest schematics ...

UART0_RX: C8 -> H10
UART0_TX: C9 -> H11

GPIO PIN Mode: NF1 -> NF2

Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

2020-11-23 03:37:33 +00:00

..

amd

soc/amd: move non-CAR linker scripts to common directory

2020-11-22 17:35:20 +00:00

cavium

soc/cavium: Drop unneeded empty lines

2020-09-22 17:14:49 +00:00

example

x86: Add a minimal example SoC along with a board

2020-10-30 21:34:18 +00:00

intel

soc/intel/alderlake: Update UART0 GPIO as per latest schematics

2020-11-23 03:37:33 +00:00

mediatek

mediatek/mt8192: memlayout: Add DRAM DMA region

2020-11-20 08:40:58 +00:00

nvidia

soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab

2020-11-09 10:31:32 +00:00

qualcomm

src: Add missing 'include <console/console.h>'

2020-11-17 09:50:24 +00:00

rockchip

src: Change bare 'unsigned' to 'unsigned int'

2020-11-16 11:03:16 +00:00

samsung

src/soc/samsung: Move common headers to "common/include/soc"

2020-10-19 07:11:32 +00:00

sifive

include/console/uart: make index parameter unsigned

2020-09-12 14:59:33 +00:00

ti

soc/ti/am335x: Fix timer implementation

2020-11-22 22:32:46 +00:00

ucb

soc/ucb/riscv: Add chip_operations stub

2020-05-28 09:30:35 +00:00