e79cb5e19d
Change-Id: I5a4e223b2e247decd30d8fb2a083be4cff6500a4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13166 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
790 lines
21 KiB
Plaintext
790 lines
21 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
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* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
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* Everything else does to the best of my knowledge... (T.P. 01/26/2015)
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*/
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/*
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* ISA portions taken from QEMU acpi-dsdt.dsl.
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*/
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/*
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* PCI link routing templates taken from ck804.asl and modified for this board
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*/
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DefinitionBlock (
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"DSDT.AML", /* Output filename */
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"DSDT", /* Signature */
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0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */
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"ASUS ", /* OEMID */
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"COREBOOT", /* TABLE ID */
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0x00000001 /* OEM Revision */
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)
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{
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#include "northbridge/amd/amdfam10/amdfam10_util.asl"
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#include "southbridge/amd/sr5650/acpi/sr5650.asl"
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/* Some global data */
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Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
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Name(OSV, Ones) /* Assume nothing */
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Name(PICM, One) /* Assume APIC */
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/* HPET enable */
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Name (HPTE, 0x1)
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/* Define power states */
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Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */
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Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 }) /* Standby */
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Name (\_S3, Package () { 0x03, 0x03, 0x00, 0x00 }) /* Suspend to RAM */
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Name (\_S4, Package () { 0x04, 0x04, 0x00, 0x00 }) /* Suspend to disk */
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Name (\_S5, Package () { 0x05, 0x05, 0x00, 0x00 }) /* Hard power off */
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/* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method (_PIC, 1, Serialized) {
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If (Arg0)
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{
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\_SB.CIRQ()
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}
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Store (Arg0, PICM)
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}
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/* _PR CPU0 is dynamically supplied by SSDT */
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/* CPU objects and _PSS entries are dynamically supplied by SSDT */
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Scope(\_GPE) { /* Start Scope GPE */
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/* General event 3 */
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Method(_L03) {
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/* Level-Triggered GPE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* General event 4 */
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Method(_L04) {
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/* Level-Triggered GPE */
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Notify (\_SB.PCI0.PBR0, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* Keyboard controller PME# */
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Method(_L08) {
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/* Level-Triggered GPE */
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Notify(\_SB.PCI0.LPC.PS2K, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.LPC.PS2M, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* USB controller PME# */
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Method(_L0B) {
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/* Level-Triggered GPE */
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Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.USB1, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.USB3, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.USB4, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.USB5, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.USB6, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* GPIO0 or GEvent8 event */
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Method(_L18) {
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/* Level-Triggered GPE */
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Notify (\_SB.PCI0.PCE1, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.PCE5, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PCI0.PCE3, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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} /* End Scope GPE */
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/* Root of the bus hierarchy */
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Scope (\_SB)
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{
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/* Top southbridge PCI device (SR5690 + SP5100) */
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Device (PCI0)
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{
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/* BUS0 root bus */
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Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */
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Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */
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Name (_ADR, 0x00180001)
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Name (_UID, 0x00)
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Name (HCIN, 0x00) // HC1
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Method (_BBN, 0, NotSerialized)
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{
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Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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}
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/* Operating System Capabilities Method */
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Method(_OSC,4)
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{
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/* Let OS control everything */
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Return (Arg3)
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}
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External (BUSN)
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External (MMIO)
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External (PCIO)
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External (SBLK)
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External (TOM1)
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External (HCLK)
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External (SBDN)
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External (HCDN)
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External (CBST)
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/* PCI Routing Tables */
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Name (PR00, Package () {
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/* PIC */
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/* Top southbridge device (SR5690) */
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/* HT Link */
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Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 },
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/* PCI-E Slot 1 (Bridge) */
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Package (0x04) { 0x0002FFFF, 0x00, LNKE, 0x00 },
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/* NIC A (Bridge) */
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Package (0x04) { 0x0009FFFF, 0x00, LNKF, 0x00 },
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/* NIC B (Bridge) */
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Package (0x04) { 0x000AFFFF, 0x00, LNKG, 0x00 },
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/* PCI-E Slot 4 (Bridge) */
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Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 },
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/* PCI-E Slot 5 (Bridge) */
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Package (0x04) { 0x000CFFFF, 0x00, LNKG, 0x00 },
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/* PCI-E Slot 3 (Bridge) */
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Package (0x04) { 0x000DFFFF, 0x00, LNKG, 0x00 },
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/* Bottom southbridge device (SP5100) */
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/* SATA 0 */
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Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 },
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/* USB 0 */
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Package (0x04) { 0x0012FFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0x0012FFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0x0012FFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0x0012FFFF, 0x03, LNKD, 0x00 },
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/* USB 1 */
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Package (0x04) { 0x0013FFFF, 0x00, LNKC, 0x00 },
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Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
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Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 },
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Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 },
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/* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */
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Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 },
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})
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Name (AR00, Package () {
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/* APIC */
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/* Top southbridge device (SR5690) */
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/* HT Link */
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 },
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/* PCI-E Slot 1 (Bridge) */
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Package (0x04) { 0x0002FFFF, 0x00, 0x00, 52 },
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/* NIC A (Bridge) */
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Package (0x04) { 0x0009FFFF, 0x00, 0x00, 53 },
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/* NIC B (Bridge) */
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Package (0x04) { 0x000AFFFF, 0x00, 0x00, 54 },
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/* PCI-E Slot 4 (Bridge) */
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Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 },
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/* PCI-E Slot 5 (Bridge) */
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Package (0x04) { 0x000CFFFF, 0x00, 0x00, 54 },
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/* PCI-E Slot 3 (Bridge) */
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Package (0x04) { 0x000DFFFF, 0x00, 0x00, 54 },
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/* Bottom southbridge device (SP5100) */
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/* SATA 0 */
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Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 },
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/* USB 0 */
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Package (0x04) { 0x0012FFFF, 0x00, 0x00, 16 },
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Package (0x04) { 0x0012FFFF, 0x01, 0x00, 17 },
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Package (0x04) { 0x0012FFFF, 0x02, 0x00, 18 },
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Package (0x04) { 0x0012FFFF, 0x03, 0x00, 19 },
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/* USB 1 */
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Package (0x04) { 0x0013FFFF, 0x00, 0x00, 18 },
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Package (0x04) { 0x0013FFFF, 0x01, 0x00, 19 },
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Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 },
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Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 },
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/* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */
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Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 },
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Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 },
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Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 },
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Package (0x04) { 0x0014FFFF, 0x03, 0x00, 19 },
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})
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Name (PR01, Package () {
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/* PIC */
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Package (0x04) { 0x1FFFF, 0x00, LNKF, 0x00 },
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Package (0x04) { 0x2FFFF, 0x00, LNKE, 0x00 },
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Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 },
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Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 },
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Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 },
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})
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Name (AR01, Package () {
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/* APIC */
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Package (0x04) { 0x1FFFF, 0x00, 0x00, 21 },
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Package (0x04) { 0x2FFFF, 0x00, 0x00, 20 },
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Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 },
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Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 },
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Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 },
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Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 },
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})
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Name (PR02, Package () {
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/* PIC */
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Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
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})
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Name (AR02, Package () {
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/* APIC */
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Package (0x04) { 0xFFFF, 0x00, 0x00, 24 },
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Package (0x04) { 0xFFFF, 0x01, 0x00, 25 },
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Package (0x04) { 0xFFFF, 0x02, 0x00, 26 },
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Package (0x04) { 0xFFFF, 0x03, 0x00, 27 },
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})
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Name (PR03, Package () {
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/* PIC */
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Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 },
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Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 },
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Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 },
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Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 },
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})
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Name (AR03, Package () {
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/* APIC */
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Package (0x04) { 0xFFFF, 0x00, 0x00, 44 },
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Package (0x04) { 0xFFFF, 0x01, 0x00, 45 },
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Package (0x04) { 0xFFFF, 0x02, 0x00, 46 },
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Package (0x04) { 0xFFFF, 0x03, 0x00, 47 },
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})
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Name (PR04, Package () {
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/* PIC */
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Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
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})
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Name (AR04, Package () {
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/* APIC */
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Package (0x04) { 0xFFFF, 0x00, 0x00, 48 },
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Package (0x04) { 0xFFFF, 0x01, 0x00, 49 },
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Package (0x04) { 0xFFFF, 0x02, 0x00, 50 },
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Package (0x04) { 0xFFFF, 0x03, 0x00, 51 },
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})
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Name (PR05, Package () {
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/* PIC */
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Package (0x04) { 0xFFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0xFFFF, 0x01, LNKE, 0x00 },
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Package (0x04) { 0xFFFF, 0x02, LNKF, 0x00 },
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Package (0x04) { 0xFFFF, 0x03, LNKG, 0x00 },
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})
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Name (AR05, Package () {
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/* APIC */
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Package (0x04) { 0xFFFF, 0x00, 0x00, 47 },
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Package (0x04) { 0xFFFF, 0x01, 0x00, 44 },
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Package (0x04) { 0xFFFF, 0x02, 0x00, 45 },
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Package (0x04) { 0xFFFF, 0x03, 0x00, 46 },
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})
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Name (PR06, Package () {
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/* PIC */
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Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
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})
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Name (AR06, Package () {
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/* APIC */
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Package (0x04) { 0xFFFF, 0x00, 0x00, 32 },
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Package (0x04) { 0xFFFF, 0x01, 0x00, 33 },
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Package (0x04) { 0xFFFF, 0x02, 0x00, 34 },
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Package (0x04) { 0xFFFF, 0x03, 0x00, 35 },
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})
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Name (PR07, Package () {
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/* PIC */
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Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 },
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Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 },
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Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 },
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Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 },
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})
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Name (AR07, Package () {
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/* APIC */
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Package (0x04) { 0xFFFF, 0x00, 0x00, 36 },
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Package (0x04) { 0xFFFF, 0x01, 0x00, 37 },
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Package (0x04) { 0xFFFF, 0x02, 0x00, 38 },
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Package (0x04) { 0xFFFF, 0x03, 0x00, 39 },
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})
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Name (PR08, Package () {
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/* PIC */
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Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
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})
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Name (AR08, Package () {
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/* APIC */
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Package (0x04) { 0xFFFF, 0x00, 0x00, 40 },
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Package (0x04) { 0xFFFF, 0x01, 0x00, 41 },
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Package (0x04) { 0xFFFF, 0x02, 0x00, 42 },
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Package (0x04) { 0xFFFF, 0x03, 0x00, 43 },
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})
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/* PCI Resource Tables */
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/* PCI Resource Settings Access */
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Method (_CRS, 0, Serialized)
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{
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Name (BUF0, ResourceTemplate ()
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{
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IO (Decode16,
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0x0CF8, // Address Range Minimum
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0x0CF8, // Address Range Maximum
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0x01, // Address Alignment
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0x08, // Address Length
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)
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x0000, // Address Range Minimum
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0x0CF7, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x0CF8, // Address Length
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,, , TypeStatic)
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})
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/* Methods below use SSDT to get actual MMIO regs
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The IO ports are from 0xd00, optionally an VGA,
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otherwise the info from MMIO is used.
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\_SB.GXXX(node, link)
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*/
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Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
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Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
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Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
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Return (Local3)
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|
}
|
|
|
|
/* PCI Routing Table Access */
|
|
Method (_PRT, 0, NotSerialized) {
|
|
If (PICM) {
|
|
Return (AR00)
|
|
} Else {
|
|
Return (PR00)
|
|
}
|
|
}
|
|
|
|
/* 0:11.0 SP5100 SATA 0 */
|
|
Device(SAT0)
|
|
{
|
|
Name (_ADR, 0x00110000) // _ADR: Address
|
|
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
|
#include "southbridge/amd/sb700/acpi/sata.asl"
|
|
}
|
|
|
|
/* 0:12.0 SP5100 USB 0 */
|
|
Device (USB0)
|
|
{
|
|
Name (_ADR, 0x00120000) // _ADR: Address
|
|
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
|
}
|
|
|
|
/* 0:12.1 SP5100 USB 1 */
|
|
Device (USB1)
|
|
{
|
|
Name (_ADR, 0x00120001) // _ADR: Address
|
|
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
|
}
|
|
|
|
/* 0:12.2 SP5100 USB 2 */
|
|
Device (USB2)
|
|
{
|
|
Name (_ADR, 0x00120002) // _ADR: Address
|
|
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
|
}
|
|
|
|
/* 0:13.0 SP5100 USB 3 */
|
|
Device (USB3)
|
|
{
|
|
Name (_ADR, 0x00130000) // _ADR: Address
|
|
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
|
}
|
|
|
|
/* 0:13.1 SP5100 USB 4 */
|
|
Device (USB4)
|
|
{
|
|
Name (_ADR, 0x00130001) // _ADR: Address
|
|
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
|
}
|
|
|
|
/* 0:13.2 SP5100 USB 5 */
|
|
Device (USB5)
|
|
{
|
|
Name (_ADR, 0x00130002) // _ADR: Address
|
|
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
|
}
|
|
|
|
/* 0:14.1 SP5100 IDE Controller */
|
|
Device (IDEC)
|
|
{
|
|
Name (_ADR, 0x00140001) // _ADR: Address
|
|
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
|
#include "southbridge/amd/sb700/acpi/ide.asl"
|
|
}
|
|
|
|
/* 0:14.3 SP5100 LPC */
|
|
Device (LPC) {
|
|
Name (_HID, EisaId ("PNP0A05"))
|
|
Name (_ADR, 0x00140003)
|
|
|
|
/* Real Time Clock Device */
|
|
Device(RTC0) {
|
|
Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
|
|
Name(BUF0, ResourceTemplate() {
|
|
IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
|
|
})
|
|
Name(BUF1, ResourceTemplate() {
|
|
IRQNoFlags() { 8 }
|
|
IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
|
|
})
|
|
Method(_CRS, 0) {
|
|
If(HPTE) {
|
|
Return(BUF0)
|
|
}
|
|
Return(BUF1)
|
|
}
|
|
}
|
|
|
|
Device(TMR) { /* Timer */
|
|
Name(_HID,EISAID("PNP0100")) /* System Timer */
|
|
Name(BUF0, ResourceTemplate() {
|
|
IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
|
|
})
|
|
Name(BUF1, ResourceTemplate() {
|
|
IRQNoFlags() { 0 }
|
|
IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
|
|
})
|
|
Method(_CRS, 0) {
|
|
If(HPTE) {
|
|
Return(BUF0)
|
|
}
|
|
Return(BUF1)
|
|
}
|
|
}
|
|
|
|
Device(SPKR) { /* Speaker */
|
|
Name(_HID,EISAID("PNP0800")) /* AT style speaker */
|
|
Name(_CRS, ResourceTemplate() {
|
|
IO(Decode16, 0x0061, 0x0061, 0, 1)
|
|
})
|
|
}
|
|
|
|
Device(PIC) {
|
|
Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
|
|
Name(_CRS, ResourceTemplate() {
|
|
IRQNoFlags() { 2 }
|
|
IO(Decode16,0x0020, 0x0020, 0, 2)
|
|
IO(Decode16,0x00A0, 0x00A0, 0, 2)
|
|
})
|
|
}
|
|
|
|
Device(MAD) { /* 8257 DMA */
|
|
Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
|
|
Name(_CRS, ResourceTemplate() {
|
|
DMA(Compatibility,BusMaster,Transfer8){4}
|
|
IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
|
|
IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
|
|
IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
|
|
IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
|
|
IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
|
|
IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
|
|
}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
|
|
}
|
|
|
|
Device(COPR) {
|
|
Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
|
|
Name(_CRS, ResourceTemplate() {
|
|
IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
|
|
IRQNoFlags(){13}
|
|
})
|
|
}
|
|
|
|
#include "../../../superio/winbond/w83667hg-a/ps2_controller.asl"
|
|
|
|
/* UART 1 */
|
|
Device (URT1)
|
|
{
|
|
Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
|
|
Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
|
|
Method (_STA, 0, NotSerialized)
|
|
{
|
|
Return (0x0f) // Always enable
|
|
}
|
|
Name (_PRS, ResourceTemplate() {
|
|
StartDependentFn(0, 1) {
|
|
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
|
|
IRQNoFlags() { 4 }
|
|
} EndDependentFn()
|
|
})
|
|
Method (_CRS, 0)
|
|
{
|
|
Return(ResourceTemplate() {
|
|
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
|
|
IRQNoFlags() { 4 }
|
|
})
|
|
}
|
|
}
|
|
}
|
|
|
|
/* High Precision Event Timer */
|
|
Device (HPET)
|
|
{
|
|
Name (_HID, EisaId ("PNP0103"))
|
|
Name (CRS, ResourceTemplate ()
|
|
{
|
|
Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400)
|
|
})
|
|
Method (_STA, 0)
|
|
{
|
|
If(HPTE) {
|
|
Return (0x0F)
|
|
}
|
|
Return (0x0)
|
|
}
|
|
Method(_CRS, 0)
|
|
{
|
|
Return(CRS)
|
|
}
|
|
}
|
|
|
|
/* 0:14.4 PCI Bridge */
|
|
Device (PBR0)
|
|
{
|
|
Name (_ADR, 0x00140004) // _ADR: Address
|
|
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
|
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
|
{
|
|
If (PICM) {
|
|
Return (AR01)
|
|
} Else {
|
|
Return (PR01)
|
|
}
|
|
}
|
|
Device (SLT1)
|
|
{
|
|
Name (_ADR, 0xFFFF) // _ADR: Address
|
|
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
|
}
|
|
}
|
|
|
|
/* 0:14.5 SP5100 USB 6 */
|
|
Device (USB6)
|
|
{
|
|
Name (_ADR, 0x00140005) // _ADR: Address
|
|
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
|
|
}
|
|
|
|
/* 2:00.0 PCIe x16 */
|
|
Device (PCE1)
|
|
{
|
|
Name (_ADR, 0x00020000) // _ADR: Address
|
|
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
|
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
|
{
|
|
If (PICM) {
|
|
Return (AR02)
|
|
} Else {
|
|
Return (PR02)
|
|
}
|
|
}
|
|
Device (SLT1)
|
|
{
|
|
Name (_ADR, 0xFFFF) // _ADR: Address
|
|
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
|
}
|
|
}
|
|
|
|
/* 1:00.0 PIKE */
|
|
Device (PIKE)
|
|
{
|
|
Name (_ADR, 0x00040000) // _ADR: Address
|
|
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
|
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
|
{
|
|
If (PICM) {
|
|
Return (AR03)
|
|
} Else {
|
|
Return (PR03)
|
|
}
|
|
}
|
|
Device (SLT1)
|
|
{
|
|
Name (_ADR, 0xFFFF) // _ADR: Address
|
|
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
|
}
|
|
}
|
|
|
|
/* 3:00.0 PCIe NIC A */
|
|
Device (NICA)
|
|
{
|
|
Name (_ADR, 0x00090000) // _ADR: Address
|
|
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
|
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
|
{
|
|
If (PICM) {
|
|
Return (AR04)
|
|
} Else {
|
|
Return (PR04)
|
|
}
|
|
}
|
|
Device (BDC1)
|
|
{
|
|
Name (_ADR, Zero) // _ADR: Address
|
|
}
|
|
}
|
|
|
|
/* 4:00.0 PCIe NIC B */
|
|
Device (NICB)
|
|
{
|
|
Name (_ADR, 0x000A0000) // _ADR: Address
|
|
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
|
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
|
{
|
|
If (PICM) {
|
|
Return (AR05)
|
|
} Else {
|
|
Return (PR05)
|
|
}
|
|
}
|
|
Device (BDC2)
|
|
{
|
|
Name (_ADR, Zero) // _ADR: Address
|
|
}
|
|
}
|
|
|
|
/* 5:00.0 PCIe x16 */
|
|
Device (PCE4)
|
|
{
|
|
Name (_ADR, 0x000B0000) // _ADR: Address
|
|
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
|
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
|
{
|
|
If (PICM) {
|
|
Return (AR06)
|
|
} Else {
|
|
Return (PR06)
|
|
}
|
|
}
|
|
Device (SLT1)
|
|
{
|
|
Name (_ADR, 0xFFFF) // _ADR: Address
|
|
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
|
}
|
|
}
|
|
|
|
/* 6:00.0 PCIe x16 */
|
|
Device (PCE5)
|
|
{
|
|
Name (_ADR, 0x000C0000) // _ADR: Address
|
|
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
|
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
|
{
|
|
If (PICM) {
|
|
Return (AR07)
|
|
} Else {
|
|
Return (PR07)
|
|
}
|
|
}
|
|
Device (SLT1)
|
|
{
|
|
Name (_ADR, 0xFFFF) // _ADR: Address
|
|
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
|
}
|
|
}
|
|
|
|
/* 7:00.0 PCIe x16 */
|
|
Device (PCE3)
|
|
{
|
|
Name (_ADR, 0x000D0000) // _ADR: Address
|
|
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
|
|
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
|
|
{
|
|
If (PICM) {
|
|
Return (AR08)
|
|
} Else {
|
|
Return (PR08)
|
|
}
|
|
}
|
|
Device (SLT1)
|
|
{
|
|
Name (_ADR, 0xFFFF) // _ADR: Address
|
|
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
|
|
}
|
|
}
|
|
}
|
|
|
|
Device (PWRB) { /* Start Power button device */
|
|
Name(_HID, EISAID("PNP0C0C"))
|
|
Name(_UID, 0xAA)
|
|
Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
|
|
Name(_STA, 0x0B) /* sata is invisible */
|
|
}
|
|
}
|
|
|
|
#include "acpi/pm_ctrl.asl"
|
|
|
|
}
|