e7fa24470d
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
40 lines
920 B
C
40 lines
920 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/romstage.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <soc/iosf.h>
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static uintptr_t smm_region_start(void)
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{
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return (iosf_bunit_read(BUNIT_SMRRL) << 20);
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}
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static size_t smm_region_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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uintptr_t cbmem_top_chipset(void)
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{
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return smm_region_start();
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
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*size = smm_region_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations.
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*/
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const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
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MTRR_TYPE_WRBACK);
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}
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