e8a3af1069
Tree is inconsistent with the use of TCO register space offsets and
related preprocessor defines. The legacy space was offset from ACPI
PM base by 0x60, but this changed with later platforms. The convenient
way is to define the TCO registers relative to its base address and
subtract 0x60 here, but this change cannot be easily done tree-wide or
in one go.
For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until
all platforms use a clean style of tco_{read,write} accessor functions
instead of {read,write}_pmbase16(), or worse, inw/outl().
Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
121 lines
2.5 KiB
Plaintext
121 lines
2.5 KiB
Plaintext
config SOC_INTEL_BROADWELL
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bool
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help
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Intel Broadwell and Haswell ULT support.
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if SOC_INTEL_BROADWELL
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config SOC_SPECIFIC_OPTIONS
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def_bool y
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select CACHE_MRC_SETTINGS
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select CPU_INTEL_HASWELL
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select INTEL_GMA_ACPI
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select MRC_SETTINGS_PROTECT
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select REG_SCRIPT
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select TCO_SPACE_NOT_YET_SPLIT
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config BROADWELL_LPDDR3
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bool
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help
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Selected by mainboards using LPDDR3 DRAM to supply mainboard-specific
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LPDDR3 DQ and DQS CPU-to-DRAM mapping info needed to perform raminit.
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config VBOOT
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_BOOTBLOCK
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config ECAM_MMCONF_BASE_ADDRESS
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default 0xf0000000
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config ECAM_MMCONF_BUS_NUMBER
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default 64
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config VGA_BIOS_ID
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string
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default "8086,0406"
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config FIXED_MCHBAR_MMIO_BASE
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default 0xfed10000
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config FIXED_DMIBAR_MMIO_BASE
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default 0xfed18000
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config FIXED_EPBAR_MMIO_BASE
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default 0xfed19000
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config DCACHE_RAM_BASE
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hex
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default 0xff7c0000
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config DCACHE_RAM_SIZE
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hex
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default 0x10000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x30000
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help
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The amount of cache-as-ram region required by the reference code.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x2000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config HAVE_MRC
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bool "Add a Memory Reference Code binary"
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help
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Select this option to add a Memory Reference Code binary to
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the resulting coreboot image.
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Note: Without this binary coreboot will not work
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if HAVE_MRC
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config MRC_FILE
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string "Intel Memory Reference Code path and filename"
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depends on HAVE_MRC
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default "mrc.bin"
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help
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The filename of the file to use as Memory Reference Code binary.
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config MRC_BIN_ADDRESS
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hex
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default 0xfffa0000
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# The UEFI System Agent binary needs to be at a fixed offset in the flash
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# and can therefore only reside in the COREBOOT fmap region
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config RO_REGION_ONLY
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string
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depends on VBOOT
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default "mrc.bin"
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endif # HAVE_MRC
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config HAVE_REFCODE_BLOB
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depends on ARCH_X86
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bool "An external reference code blob should be put into cbfs."
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default n
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help
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The reference code blob will be placed into cbfs.
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if HAVE_REFCODE_BLOB
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config REFCODE_BLOB_FILE
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string "Path and filename to reference code blob."
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default "refcode.elf"
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help
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The path and filename to the file to be added to cbfs.
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endif # HAVE_REFCODE_BLOB
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source "src/soc/intel/broadwell/pch/Kconfig"
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endif
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