Change-Id: If25ed7b5cc545abcbf16af66173058dde75260f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41703 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
71 lines
1.4 KiB
Plaintext
71 lines
1.4 KiB
Plaintext
if BOARD_INTEL_JASPERLAKE_RVP || BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_DA7219
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_MAX98373
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select DRIVERS_SPI_ACPI
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select DRIVERS_USB_ACPI
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select EC_ACPI
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select GENERIC_SPD_BIN
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select SOC_INTEL_JASPERLAKE
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config MAINBOARD_DIR
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string
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default "intel/jasperlake_rvp"
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config VARIANT_DIR
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string
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default "jslrvp" if BOARD_INTEL_JASPERLAKE_RVP || BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
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config MAINBOARD_PART_NUMBER
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string
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default "jslrvp"
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config MAINBOARD_FAMILY
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string
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default "Intel_jslrvp"
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config MAX_CPUS
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int
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default 8
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config DEVICETREE
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string
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config DIMM_SPD_SIZE
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int
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default 512
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config CHROMEOS
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bool
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default y
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2
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config UART_FOR_CONSOLE
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int
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default 2 if INTEL_LPSS_UART_FOR_CONSOLE
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default 0
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 45 # GPE0_DW1_13 (GPP_H13)
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endif
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