e9b862eb2c
Remove the old Hudson-specific SMM command port definitions and use the ones in cpu/x86/smm.h. Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
127 lines
3.0 KiB
C
127 lines
3.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <bootstate.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <amd_pci_util.h>
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#include <soc/southbridge.h>
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#include <soc/smbus.h>
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#include <soc/smi.h>
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#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)
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#include <fchec.h>
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#endif
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int acpi_get_sleep_type(void)
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{
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u16 tmp = inw(ACPI_PM1_CNT_BLK);
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tmp = ((tmp & (7 << 10)) >> 10);
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return (int)tmp;
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}
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void pm_write8(u8 reg, u8 value)
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{
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write8((void *)(PM_MMIO_BASE + reg), value);
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}
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u8 pm_read8(u8 reg)
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{
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return read8((void *)(PM_MMIO_BASE + reg));
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}
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void pm_write16(u8 reg, u16 value)
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{
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write16((void *)(PM_MMIO_BASE + reg), value);
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}
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u16 pm_read16(u16 reg)
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{
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return read16((void *)(PM_MMIO_BASE + reg));
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}
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void sb_enable(device_t dev)
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{
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printk(BIOS_DEBUG, "%s\n", __func__);
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}
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static void sb_init_acpi_ports(void)
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{
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/* We use some of these ports in SMM regardless of whether or not
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* ACPI tables are generated. Enable these ports indiscriminately.
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*/
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pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
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pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
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pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
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pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
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/* CpuControl is in \_PR.CP00, 6 bytes */
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pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
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pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
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enable_acpi_cmd_smi();
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} else {
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pm_write16(PM_ACPI_SMI_CMD, 0);
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}
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/* AcpiDecodeEnable, When set, SB uses the contents of the PM registers
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* at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn
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*/
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pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2));
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}
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void southbridge_init(void *chip_info)
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{
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sb_init_acpi_ports();
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}
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void southbridge_final(void *chip_info)
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{
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#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)
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agesawrapper_fchecfancontrolservice();
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#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
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enable_imc_thermal_zone();
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#endif
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#endif
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}
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/*
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* Update the PCI devices with a valid IRQ number
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* that is set in the mainboard PCI_IRQ structures.
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*/
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static void set_pci_irqs(void *unused)
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{
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/* Write PCI_INTR regs 0xC00/0xC01 */
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write_pci_int_table();
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/* Write IRQs for all devicetree enabled devices */
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write_pci_cfg_irqs();
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}
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/*
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* Hook this function into the PCI state machine
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* on entry into BS_DEV_ENABLE.
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*/
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
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