ea942169f9
Cherry-pick from Chromium: 55c0eb3 [Lili: Set new thermal parameters] Set new parameters of DPTF for both Lars and Lili. The acoustic will have higher 1.6dB in transition mode, when using Lili fan table on Lars. Original-Change-Id: I730ac483e2a6d43c8dcfe94da6761194c14f3163 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
138 lines
4.0 KiB
Plaintext
138 lines
4.0 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define DPTF_CPU_PASSIVE 94
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#define DPTF_CPU_CRITICAL 99
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#define DPTF_CPU_ACTIVE_AC0 90
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#define DPTF_CPU_ACTIVE_AC1 70
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#define DPTF_TSR0_SENSOR_ID 2
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#define DPTF_TSR0_SENSOR_NAME "TMP432_CPU_bottom"
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#define DPTF_TSR0_PASSIVE 65
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#define DPTF_TSR0_CRITICAL 70
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#define DPTF_TSR0_ACTIVE_AC0 60
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#define DPTF_TSR0_ACTIVE_AC1 48
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#define DPTF_TSR0_ACTIVE_AC2 42
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#define DPTF_TSR0_ACTIVE_AC3 39
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#define DPTF_TSR0_ACTIVE_AC4 36
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#define DPTF_TSR0_ACTIVE_AC5 34
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#define DPTF_TSR0_ACTIVE_AC6 32
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
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#define DPTF_TSR1_PASSIVE 65
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#define DPTF_TSR1_CRITICAL 70
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#define DPTF_TSR2_SENSOR_ID 0
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#define DPTF_TSR2_SENSOR_NAME "TMP432_Internal"
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#define DPTF_TSR2_PASSIVE 65
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#define DPTF_TSR2_CRITICAL 70
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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/* Charger performance states, board-specific values from charger and EC */
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Name (CHPS, Package () {
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Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
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Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
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Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
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Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
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Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
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})
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#ifdef DPTF_ENABLE_FAN_CONTROL
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/* DFPS: Fan Performance States */
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Name (DFPS, Package () {
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0, // Revision
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/*
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* TODO : Need to update this Table after characterization.
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* These are initial reference values.
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*/
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/* Control, Trip Point, Speed, NoiseLevel, Power */
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Package () {100, 0xFFFFFFFF, 4986, 220, 2200},
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Package () {90, 0xFFFFFFFF, 4804, 180, 1800},
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Package () {80, 0xFFFFFFFF, 4512, 145, 1450},
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Package () {70, 0xFFFFFFFF, 4204, 115, 1150},
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Package () {60, 0xFFFFFFFF, 3838, 90, 900},
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Package () {50, 0xFFFFFFFF, 3402, 65, 650},
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Package () {40, 0xFFFFFFFF, 2904, 45, 450},
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Package () {30, 0xFFFFFFFF, 2337, 30, 300},
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Package () {20, 0xFFFFFFFF, 1608, 15, 150},
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Package () {10, 0xFFFFFFFF, 800, 10, 100},
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Package () {0, 0xFFFFFFFF, 0, 0, 50}
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})
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Name (DART, Package () {
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/* Fan effect on CPU */
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0, // Revision
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Package () {
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/*
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* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
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* AC7, AC8, AC9
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*/
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\_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 0, 0, 0, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 90, 75, 62, 55, 47,
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41, 0, 0, 0
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}
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})
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#endif
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 0 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
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#ifdef DPTF_ENABLE_CHARGER
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/* Charger Effect on Temp Sensor 1 */
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
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#endif
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/* CPU Effect on Temp Sensor 1 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 2 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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1600, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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25000, /* PowerLimitMinimum */
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25000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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/* Include DPTF */
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#include <soc/intel/skylake/acpi/dptf/dptf.asl>
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