eaab6305be
Richland - Microarchitecture: Piledriver Core stepping: RL-A1 CPUID: 610F31 Change-Id: I790085fbf36d836c903dcce77d794abb8578712b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7537 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
46 lines
1.2 KiB
C
46 lines
1.2 KiB
C
/*
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* udelay() impementation for SMI handlers
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* This is neat in that it never writes to hardware registers, and thus does not
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* modify the state of the hardware while servicing SMIs.
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*
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* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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* Subject to the GNU GPL v2, or (at your option) any later version.
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*/
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include <delay.h>
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#include <stdint.h>
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void udelay(uint32_t us)
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{
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uint8_t fid, did, pstate_idx;
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uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks;
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msr_t msr;
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const uint64_t tsc_base = 100000000;
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/* Get initial timestamp before we do the math */
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tsc_start = rdtscll();
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/* Get the P-state. This determines which MSR to read */
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msr = rdmsr(0xc0010063);
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pstate_idx = msr.lo & 0x07;
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/* Get FID and VID for current P-State */
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msr = rdmsr(0xc0010064 + pstate_idx);
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/* Extract the FID and VID values */
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fid = msr.lo & 0x3f;
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did = (msr.lo >> 6) & 0x7;
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/* Calculate the CPU clock (from base freq of 100MHz) */
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tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
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/* Now go on and wait */
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tsc_wait_ticks = (tsc_clock / 1000000) * us;
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do {
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tsc_now = rdtscll();
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} while (tsc_now - tsc_wait_ticks < tsc_start);
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}
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