This provides support to update energy performance preference value. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _CPU_INTEL_COMMON_H
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#define _CPU_INTEL_COMMON_H
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#include <types.h>
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#include <acpi/acpigen.h>
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void set_vmx_and_lock(void);
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void set_feature_ctrl_vmx(void);
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void set_feature_ctrl_vmx_arg(bool enable);
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void set_feature_ctrl_lock(void);
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/*
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* Init CPPC block with MSRs for Intel Enhanced Speed Step Technology.
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* Version 2 is suggested--this function's implementation of version 3
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* may have room for improvement.
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*/
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struct cppc_config;
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void cpu_init_cppc_config(struct cppc_config *config, u32 version);
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/*
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* Returns true if CPU supports Hyper-Threading.
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*/
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bool intel_ht_supported(void);
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/*
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* Returns true if it's not thread 0 on a hyperthreading enabled core.
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*/
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bool intel_ht_sibling(void);
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/*
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* Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended changes
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* to the enablement state as suggested in Intel document 325384-070US.
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*/
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void set_aesni_lock(void);
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/* Enable local CPU APIC TPR (Task Priority Register) updates */
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void enable_lapic_tpr(void);
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/* Enable DCA (Direct Cache Access) */
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void configure_dca_cap(void);
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/*
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* Set EPB (Energy Performance Bias)
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* Possible values are 0 (performance) to 15 (powersave).
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*/
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void set_energy_perf_bias(u8 policy);
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/*
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* Check energy performance preference and HWP capabilities from Thermal and
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* Power Management Leaf CPUID.
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*/
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bool check_energy_perf_cap(void);
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/*
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* Set the IA32_HWP_REQUEST Energy-Performance Preference bits on the logical
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* thread. 0 is a hint to the HWP to prefer performance, and 255 is a hint to
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* prefer energy efficiency.
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*/
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void set_energy_perf_pref(u8 pref);
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/*
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* Instructs the CPU to use EPP hints. This means that any energy policies set
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* up in `set_energy_perf_bias` will be ignored afterwards.
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*/
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void enable_energy_perf_pref(void);
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#endif
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