eb2fc04c97
This supports the Foxconn d41s, d42s, d51s, d52s. The following is tested (SeaBIOS 1.12 + Linux 4.9) and works: - COM1 - S3 resume (with SeaBIOS needs sercon disabled) - Native graphic init on VGA output - SATA - USB - Ethernet - PS2 keyboard The base for this mainboard port was the Intel D510MO port. Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28227 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
42 lines
1.1 KiB
Plaintext
42 lines
1.1 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20090419 // OEM revision
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)
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{
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#include "acpi/platform.asl"
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#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
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#include <cpu/intel/speedstep/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <northbridge/intel/pineview/acpi/pineview.asl>
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#include <southbridge/intel/i82801gx/acpi/ich7.asl>
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}
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}
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/* Chipset specific sleep states */
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#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
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}
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