056fbe49ff
Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/smm_reloc.h>
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#include <bootstate.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/pmc.h>
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/* Save the gpio route register. The settings are committed from
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* smm_southbridge_enable_smi(). */
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static uint32_t gpio_route;
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void smm_southcluster_save_gpio_route(uint32_t route)
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{
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gpio_route = route;
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}
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void smm_southbridge_clear_state(void)
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{
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uint32_t smi_en;
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/* Log events from chipset before clearing */
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if (CONFIG(ELOG))
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southcluster_log_state();
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printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
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printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());
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smi_en = inl(get_pmbase() + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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/* Dump and clear status registers */
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clear_smi_status();
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clear_pm1_status();
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clear_tco_status();
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clear_gpe_status();
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clear_alt_status();
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clear_pmc_status();
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}
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static void smm_southcluster_route_gpios(void)
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{
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u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
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const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
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uint32_t alt_gpio_reg = 0;
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uint32_t route_reg = gpio_route;
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int i;
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printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg);
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/* Start the routing for the specific gpios. */
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write32(gpio_rout, route_reg);
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/* Enable SMIs for the gpios that are set to trigger the SMI. */
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for (i = 0; i < 16; i++) {
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if ((route_reg & ROUTE_MASK) == ROUTE_SMI) {
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alt_gpio_reg |= (1 << i);
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}
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route_reg >>= 2;
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}
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printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg);
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outl(alt_gpio_reg, alt_gpio_smi);
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}
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void smm_southbridge_enable_smi(void)
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{
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printk(BIOS_DEBUG, "Enabling SMIs.\n");
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/* Configure events Disable pcie wake. */
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enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
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disable_gpe(PME_B0_EN);
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/* Set up the GPIO route. */
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smm_southcluster_route_gpios();
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/* Enable SMI generation:
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* - on APMC writes (io 0xb2)
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* - on writes to SLP_EN (sleep states)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on TCO events
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* - on microcontroller writes (io 0x62/0x66)
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*/
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enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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/*
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* Issue SMI to set the gnvs pointer in SMM.
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* tcg and smi1 are unused.
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*
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* EAX = APM_CNT_GNVS_UPDATE
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* EBX = gnvs pointer
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* EDX = APM_CNT
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*/
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asm volatile (
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"outb %%al, %%dx\n\t"
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: /* ignore result */
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: "a" (APM_CNT_GNVS_UPDATE),
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"b" ((uint32_t)gnvs),
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"d" (APM_CNT)
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);
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}
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static void finalize_chipset(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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/* Lock sleep stretching policy and set SMI lock. */
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write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2),
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read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2))
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| SLPSX_STR_POL_LOCK | SMI_LOCK);
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outb(APM_CNT_FINALIZE, APM_CNT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL);
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