ebace9f250
This change adds and updates headers in all of the southbridge files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all southbridge directories. Change-Id: I09614730bfd4db923dda103bd07bab02836a4c92 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
104 lines
2.6 KiB
C
104 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* (C) 2004 Linux Networx
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <delay.h>
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#include "amd8111.h"
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#define CMD3 0x54
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typedef enum {
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VAL3 = (1 << 31), /* VAL bit for byte 3 */
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VAL2 = (1 << 23), /* VAL bit for byte 2 */
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VAL1 = (1 << 15), /* VAL bit for byte 1 */
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VAL0 = (1 << 7), /* VAL bit for byte 0 */
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}VAL_BITS;
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typedef enum {
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/* VAL3 */
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ASF_INIT_DONE_ALIAS = (1 << 29),
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/* VAL2 */
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JUMBO = (1 << 21),
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VSIZE = (1 << 20),
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VLONLY = (1 << 19),
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VL_TAG_DEL = (1 << 18),
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/* VAL1 */
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EN_PMGR = (1 << 14),
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INTLEVEL = (1 << 13),
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FORCE_FULL_DUPLEX = (1 << 12),
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FORCE_LINK_STATUS = (1 << 11),
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APEP = (1 << 10),
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MPPLBA = (1 << 9),
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/* VAL0 */
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RESET_PHY_PULSE = (1 << 2),
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RESET_PHY = (1 << 1),
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PHY_RST_POL = (1 << 0),
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}CMD3_BITS;
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static void nic_init(struct device *dev)
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{
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struct southbridge_amd_amd8111_config *conf;
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struct resource *resource;
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u8 *mmio;
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conf = dev->chip_info;
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resource = find_resource(dev, PCI_BASE_ADDRESS_0);
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mmio = res2mmio(resource, 0, 0);
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/* Hard Reset PHY */
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printk(BIOS_DEBUG, "Resetting PHY... ");
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if (conf->phy_lowreset) {
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write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
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} else {
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write32((mmio + CMD3), VAL0 | RESET_PHY);
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}
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mdelay(15);
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write32((mmio + CMD3), RESET_PHY);
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printk(BIOS_DEBUG, "Done\n");
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}
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static void lpci_set_subsystem(struct device *dev, unsigned vendor,
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unsigned device)
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{
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pci_write_config32(dev, 0xc8,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = lpci_set_subsystem,
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};
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static struct device_operations nic_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = nic_init,
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.scan_bus = 0,
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.enable = amd8111_enable,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver nic_driver __pci_driver = {
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.ops = &nic_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_NIC,
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};
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