55189c9d33
Change-Id: I2858fdf74e782f425d56653491cdebe83c185d19 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
156 lines
3.7 KiB
Plaintext
156 lines
3.7 KiB
Plaintext
# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# X200 Liberated Flash Descriptor
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# Layout:
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# 0x0000 - 0x1000 : IFD
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# 0x1000 - 0x3000 : GbE x2
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# 0x3000 - ROMSIZE : BIOS
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{
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"fd_signature" = 0xff0a55a,
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"flmap0_fcba" = 0x1,
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"flmap0_nc" = 0x0,
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"flmap0_reserved0" = 0x0,
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"flmap0_frba" = 0x4,
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"flmap0_nr" = 0x3,
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"flmap0_reserved1" = 0x0,
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"flmap1_fmba" = 0x6,
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"flmap1_nm" = 0x2,
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"flmap1_reserved" = 0x0,
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"flmap1_fisba" = 0x10,
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"flmap1_isl" = 0x2,
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"flmap2_fmsba" = 0x20,
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"flmap2_msl" = 0x1,
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"flmap2_reserved" = 0x0,
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"flcomp_density1" = 0x4,
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"flcomp_density2" = 0x2,
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"flcomp_reserved0" = 0x0,
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"flcomp_reserved1" = 0x0,
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"flcomp_reserved2" = 0x0,
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"flcomp_readclockfreq" = 0x0,
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"flcomp_fastreadsupp" = 0x1,
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"flcomp_fastreadfreq" = 0x1,
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"flcomp_w_eraseclkfreq" = 0x0,
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"flcomp_r_statclkfreq" = 0x0,
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"flcomp_reserved3" = 0x0,
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"flill" = 0x0,
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"flbp" = 0x0,
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"comp_padding"[0x24] = 0xff,
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"flreg0_base" = 0x0,
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"flreg0_reserved0" = 0x0,
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"flreg0_limit" = 0x0,
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"flreg0_reserved1" = 0x0,
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"flreg1_base" = 0x3,
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"flreg1_reserved0" = 0x0,
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"flreg1_limit" = 0x7ff,
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"flreg1_reserved1" = 0x0,
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"flreg2_base" = 0x1fff,
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"flreg2_reserved0" = 0x0,
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"flreg2_limit" = 0x0,
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"flreg2_reserved1" = 0x0,
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"flreg3_base" = 0x1,
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"flreg3_reserved0" = 0x0,
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"flreg3_limit" = 0x2,
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"flreg3_reserved1" = 0x0,
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"flreg4_base" = 0x1fff,
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"flreg4_reserved0" = 0x0,
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"flreg4_limit" = 0x0,
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"flreg4_reserved1" = 0x0,
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"flreg_padding"[12] = 0xff,
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"flmstr1_requesterid" = 0x0,
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"flmstr1_r_fd" = 0x1,
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"flmstr1_r_bios" = 0x1,
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"flmstr1_r_me" = 0x1,
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"flmstr1_r_gbe" = 0x1,
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"flmstr1_r_pd" = 0x1,
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"flmstr1_r_reserved" = 0x0,
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"flmstr1_w_fd" = 0x1,
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"flmstr1_w_bios" = 0x1,
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"flmstr1_w_me" = 0x1,
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"flmstr1_w_gbe" = 0x1,
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"flmstr1_w_pd" = 0x1,
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"flmstr1_w_reserved" = 0x0,
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"flmstr2_requesterid" = 0x0,
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"flmstr2_r_fd" = 0x0,
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"flmstr2_r_bios" = 0x0,
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"flmstr2_r_me" = 0x0,
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"flmstr2_r_gbe" = 0x0,
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"flmstr2_r_pd" = 0x0,
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"flmstr2_r_reserved" = 0x0,
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"flmstr2_w_fd" = 0x0,
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"flmstr2_w_bios" = 0x0,
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"flmstr2_w_me" = 0x0,
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"flmstr2_w_gbe" = 0x0,
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"flmstr2_w_pd" = 0x0,
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"flmstr2_w_reserved" = 0x0,
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"flmstr3_requesterid" = 0x218,
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"flmstr3_r_fd" = 0x0,
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"flmstr3_r_bios" = 0x0,
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"flmstr3_r_me" = 0x0,
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"flmstr3_r_gbe" = 0x1,
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"flmstr3_r_pd" = 0x0,
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"flmstr3_r_reserved" = 0x0,
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"flmstr3_w_fd" = 0x0,
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"flmstr3_w_bios" = 0x0,
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"flmstr3_w_me" = 0x0,
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"flmstr3_w_gbe" = 0x1,
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"flmstr3_w_pd" = 0x0,
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"flmstr3_w_reserved" = 0x0,
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"flmstr_padding"[0x94] = 0xff,
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"ich0_medisable" = 0x1,
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"ich0_reserved0" = 0x4,
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"ich0_tcomode" = 0x1,
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"ich0_mesmbusaddr" = 0x64,
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"ich0_bmcmode" = 0x0,
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"ich0_trippointsel" = 0x0,
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"ich0_reserved1" = 0x0,
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"ich0_integratedgbe" = 0x1,
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"ich0_lanphy" = 0x1,
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"ich0_reserved2" = 0x0,
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"ich0_dmireqiddisable" = 0x0,
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"ich0_me2smbusaddr" = 0x0,
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"ich1_dynclk_nmlink" = 0x1,
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"ich1_dynclk_smlink" = 0x1,
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"ich1_dynclk_mesmbus" = 0x1,
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"ich1_dynclk_sst" = 0x1,
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"ich1_reserved0" = 0x0,
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"ich1_nmlink_npostreqs" = 0x1,
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"ich1_reserved1" = 0x0,
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"ich1_reserved2" = 0x0,
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"ichstrap_padding"[0xf8] = 0xff,
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"mch0_medisable" = 0x1,
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"mch0_mebootfromflash" = 0x0,
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"mch0_tpmdisable" = 0x1,
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"mch0_reserved0" = 0x7,
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"mch0_spifingerprinton" = 0x1,
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"mch0_mealtdisable" = 0x0,
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"mch0_reserved1" = 0xff,
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"mch0_reserved2" = 0xffff,
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"mchstrap_padding"[0xcdc] = 0xff,
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"mevscc_jid0" = 0x1720c2,
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"mevscc_vscc0" = 0x20052005,
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"mevscc_jid1" = 0x1730ef,
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"mevscc_vscc1" = 0x20052005,
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"mevscc_jid2" = 0x481f,
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"mevscc_vscc2" = 0x20152015,
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"mevscc_padding"[4] = 0xff,
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"mevscc_tablebase" = 0xee,
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"mevscc_tablelength" = 0x6,
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"mevscc_reserved" = 0x0,
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"oem_magic0" = 0x4c,
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"oem_magic1" = 0x49,
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"oem_magic2" = 0x42,
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"oem_magic3" = 0x45,
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"oem_magic4" = 0x52,
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"oem_magic5" = 0x41,
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"oem_magic6" = 0x54,
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"oem_magic7" = 0x45,
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"oem_padding"[0xf8] = 0xff
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}
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