system76-coreboot

Files

Harsha B R ec0a85b580 mb/intel/mtlrvp: Configure GPIO Tier-1 GPEs for MTL-RVP

Configure GPIO Tier-1 GPE's that defines the route for GPE
events for MTL-RVP. Configure GPE route as below,
PMC_GPE0_DW0 -> GPP_B
PMC_GPE0_DW1 -> GPP_D
PMC_GPE0_DW2 -> GPP_E

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to ChromeOS
using subsequent patches in the train

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

2022-12-29 07:10:46 +00:00

acpi

tree/acpi: Replace constant "Zero" with actual number

2022-12-27 09:06:47 +00:00

arch

{acpi,arch,soc}/acpi: Replace constant "One" with actual number

2022-12-27 09:05:15 +00:00

commonlib

coreboot_tables: Make existing alignment conventions more explicit

2022-12-22 15:34:28 +00:00

console

lib: Hook up libhwbase in romstage