8aafbd8252
Use of device_t has been abandoned in ramstage. Change-Id: Iaca908cc9ba5d11468a97d2f43911db925b93f1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
302 lines
7.9 KiB
C
302 lines
7.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/i8259.h>
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#include <pc80/keyboard.h>
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#include <pc80/isa-dma.h>
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#include <cpu/x86/lapic.h>
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#include <arch/ioapic.h>
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#include <stdlib.h>
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#define ACPI_IO_BASE 0x400
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static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 };
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static const unsigned char usb_pins[4] = { 'A', 'B', 'C', 'D' };
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static const unsigned char vga_pins[4] = { 'A', 'B', 'C', 'D' };
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static const unsigned char slot_pins[4] = { 'B', 'C', 'D', 'A' };
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static const unsigned char ac97_pins[4] = { 'B', 'C', 'D', 'A' };
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static unsigned char *pin_to_irq(const unsigned char *pin)
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{
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static unsigned char irqs[4];
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int i;
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for (i = 0; i < 4; i++)
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irqs[i] = pci_irqs[pin[i] - 'A'];
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return irqs;
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}
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static void pci_routing_fixup(struct device *dev)
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{
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printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev);
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/* set up PCI IRQ routing */
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pci_write_config8(dev, 0x55, pci_irqs[0] << 4);
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pci_write_config8(dev, 0x56, pci_irqs[1] | (pci_irqs[2] << 4));
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pci_write_config8(dev, 0x57, pci_irqs[3] << 4);
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/* Assigning IRQs */
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printk(BIOS_DEBUG, "Setting up USB interrupts.\n");
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pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins));
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printk(BIOS_DEBUG, "Setting up VGA interrupts.\n");
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pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins));
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printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n");
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pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins));
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// more?
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printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n");
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pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins));
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}
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/*
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* Set up the power management capabilities directly into ACPI mode. This
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* avoids having to handle any System Management Interrupts (SMI's) which I
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* can't figure out how to do !!!!
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*/
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static void setup_pm(struct device *dev)
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{
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/* Debounce LID and PWRBTN# Inputs for 16ms. */
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pci_write_config8(dev, 0x80, 0x20);
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/* Set ACPI base address to IO ACPI_IO_BASE */
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pci_write_config16(dev, 0x88, ACPI_IO_BASE | 1);
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/* set ACPI irq to 9 */
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pci_write_config8(dev, 0x82, 0x49);
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/* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */
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pci_write_config16(dev, 0x84, 0x609a);
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/* SMI output level to low, 7.5us throttle clock */
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pci_write_config8(dev, 0x8d, 0x18);
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/* GP Timer Control 1s */
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pci_write_config8(dev, 0x93, 0x88);
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/* Power Well */
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pci_write_config8(dev, 0x94, 0x20); // 0x20??
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/* 7 = stp to sust delay 1msec
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* 6 = SUSST# Deasserted Before PWRGD for STD
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*/
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pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
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/* Disable GP2 & GP3 Timer */
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pci_write_config8(dev, 0x98, 0);
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/* GP2 Timer Counter */
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pci_write_config8(dev, 0x99, 0xfb);
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/* GP3 Timer Counter */
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/* Multi Function Select 1 */
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pci_write_config8(dev, 0xe4, 0x00);
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/* Multi Function Select 2 */
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pci_write_config8(dev, 0xe5, 0x41); //??
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/* Enable ACPI access (and setup like award) */
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pci_write_config8(dev, 0x81, 0x84);
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/* Clear status events. */
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outw(0xffff, ACPI_IO_BASE + 0x00);
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outw(0xffff, ACPI_IO_BASE + 0x20);
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outw(0xffff, ACPI_IO_BASE + 0x28);
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outl(0xffffffff, ACPI_IO_BASE + 0x30);
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/* Disable SCI on GPIO. */
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outw(0x0, ACPI_IO_BASE + 0x22);
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/* Disable SMI on GPIO. */
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outw(0x0, ACPI_IO_BASE + 0x24);
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/* Disable all global enable SMIs. */
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outw(0x0, ACPI_IO_BASE + 0x2a);
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/* All SMI off, both IDE buses ON, PSON rising edge. */
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outw(0x0, ACPI_IO_BASE + 0x2c);
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/* Primary activity SMI disable. */
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outl(0x0, ACPI_IO_BASE + 0x34);
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/* GP timer reload on none. */
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outl(0x0, ACPI_IO_BASE + 0x38);
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/* Disable extended IO traps. */
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outb(0x0, ACPI_IO_BASE + 0x42);
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/* SCI is generated for RTC/pwrBtn/slpBtn. */
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outw(0x0001, ACPI_IO_BASE + 0x04);
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/* Allow SLP# signal to assert LDTSTOP_L.
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* Will work for C3 and for FID/VID change.
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*/
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outb(0x1, ACPI_IO_BASE + 0x11);
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}
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static void cx700_set_lpc_registers(struct device *dev)
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{
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unsigned char enables;
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printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
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// enable the internal I/O decode
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enables = pci_read_config8(dev, 0x6C);
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enables |= 0x80;
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pci_write_config8(dev, 0x6C, enables);
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// Map 4MB of FLASH into the address space
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// Set bit 6 of 0x40, because Award does it (IO recovery time)
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// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
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// interrupts can be properly marked as level triggered.
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enables = pci_read_config8(dev, 0x40);
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enables |= 0x44;
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pci_write_config8(dev, 0x40, enables);
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/* DMA Line buffer control */
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enables = pci_read_config8(dev, 0x42);
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enables |= 0xf0;
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pci_write_config8(dev, 0x42, enables);
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/* I/O recovery time */
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pci_write_config8(dev, 0x4c, 0x44);
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/* ROM memory cycles go to LPC. */
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pci_write_config8(dev, 0x59, 0x80);
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/* Enable SM dynamic clock gating */
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pci_write_config8(dev, 0x5b, 0x01);
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/* Set Read Pass Write Control Enable */
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pci_write_config8(dev, 0x48, 0x0c);
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/* Set SM Misc Control: Enable Internal APIC . */
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enables = pci_read_config8(dev, 0x58);
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enables |= 1 << 6;
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pci_write_config8(dev, 0x58, enables);
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enables = pci_read_config8(dev, 0x4d);
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enables |= 1 << 3;
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pci_write_config8(dev, 0x4d, enables);
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/* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */
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enables = pci_read_config8(dev, 0x4f);
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enables |= 0x08;
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pci_write_config8(dev, 0x4f, enables);
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/* enable KBC configuration */
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pci_write_config8(dev, 0x51, 0x1f);
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/* enable serial irq */
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pci_write_config8(dev, 0x52, 0x9);
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/* dma */
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pci_write_config8(dev, 0x53, 0x00);
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// Power management setup
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setup_pm(dev);
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/* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
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pci_write_config8(dev, 0x40, 0x54);
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/* Enable HPET timer */
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pci_write_config32(dev, 0x68, (1 << 31) | (CONFIG_HPET_ADDRESS >> 8));
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}
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static void cx700_read_resources(struct device *dev)
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{
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struct resource *res;
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/* Make sure we call our childrens set/enable functions - these
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* are not called unless this device has a resource to set.
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*/
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pci_dev_read_resources(dev);
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res = new_resource(dev, 1);
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res->base = 0x0UL;
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res->size = 0x400UL;
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res->limit = 0xffffUL;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, 3); /* IOAPIC */
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res->base = IO_APIC_ADDR;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static void cx700_set_resources(struct device *dev)
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{
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struct resource *resource;
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resource = find_resource(dev, 1);
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resource->flags |= IORESOURCE_STORED;
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pci_dev_set_resources(dev);
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}
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static void cx700_enable_resources(struct device *dev)
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{
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/* Enable SuperIO decoding */
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pci_dev_enable_resources(dev);
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}
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static void cx700_lpc_init(struct device *dev)
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{
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cx700_set_lpc_registers(dev);
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#if IS_ENABLED(CONFIG_IOAPIC)
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#define IO_APIC_ID 2
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setup_ioapic(VIO_APIC_VADDR, IO_APIC_ID);
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#endif
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/* Initialize interrupts */
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pci_routing_fixup(dev);
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/* make sure interupt controller is configured before keyboard init */
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setup_i8259();
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/* Start the Real Time Clock */
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cmos_init(0);
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/* Initialize isa dma */
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isa_dma_init();
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/* Initialize keyboard controller */
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pc_keyboard_init(NO_AUX_DEVICE);
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}
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static struct device_operations cx700_lpc_ops = {
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.read_resources = cx700_read_resources,
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.set_resources = cx700_set_resources,
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.enable_resources = cx700_enable_resources,
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.init = cx700_lpc_init,
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.scan_bus = scan_lpc_bus,
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};
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static const struct pci_driver lpc_driver __pci_driver = {
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.ops = &cx700_lpc_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = 0x8324,
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};
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