ece26961b9
Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
79 lines
2.1 KiB
C
79 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/speedstep.h>
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#include "model_206ax.h"
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/* MSR Documentation based on
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* "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
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* Document Number 504790
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* Revision 1.6.0, June 2012 */
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static void msr_set_bit(unsigned int reg, unsigned int bit)
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{
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msr_t msr = rdmsr(reg);
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if (bit < 32) {
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if (msr.lo & (1 << bit))
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return;
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msr.lo |= 1 << bit;
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} else {
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if (msr.hi & (1 << (bit - 32)))
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return;
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msr.hi |= 1 << (bit - 32);
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}
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wrmsr(reg, msr);
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}
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void intel_model_206ax_finalize_smm(void)
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{
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/* Lock C-State MSR */
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msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
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/* Lock AES-NI only if supported */
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if (cpuid_ecx(1) & (1 << 25))
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msr_set_bit(MSR_FEATURE_CONFIG, 0);
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#ifdef LOCK_POWER_CONTROL_REGISTERS
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/*
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* Lock the power control registers.
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*
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* These registers can be left unlocked if modifying power
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* limits from the OS is desirable. Modifying power limits
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* from the OS can be especially useful for experimentation
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* during early phases of system bringup while the thermal
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* power envelope is being proven.
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*/
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msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
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msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
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msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
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msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
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msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
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#endif
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/* Lock TM interrupts - route thermal events to all processors */
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msr_set_bit(MSR_MISC_PWR_MGMT, 22);
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/* Lock memory configuration to protect SMM */
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msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
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}
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