ecf2eb463f
This is a sad story. We have three different code paths for sandybridge and ivybridge: proper native path, google MRC path, and, everyone's favorite: Intel FSP path. For the purpose of this patch, the FSP path lives in its own little world, and doesn't concern us. Since MRC was first, when native files and variables were added, they were suffixed with "_native" to separate them from the existing code. This can cause confusion, as the suffix might make the native files seem parasitical. This has been bothering me for many months. MRC should be the parasitical path, especially since we fully support native init, and it works more reliably, on a wider range of hardware. There have been a few board ports that never made it to coreboot.org because MRC would hang. gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so the effort was abandoned at first. Once the native path became available, the effort was restarted and the board is now supported. In honor of the hackers and pioneers who made the native code possible, rename things so that their effort is the first class citizen. Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11788 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
123 lines
3.4 KiB
C
123 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <kconfig.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "pch.h"
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#include <device/pci_ehci.h>
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#include <arch/io.h>
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static void usb_ehci_init(struct device *dev)
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{
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u32 reg32;
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/* Disable Wake on Disconnect in RMH */
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reg32 = RCBA32(0x35b0);
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reg32 |= 0x22;
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RCBA32(0x35b0) = reg32;
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printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
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/* For others, done in MRC. */
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#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)
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pci_write_config32(dev, 0x84, 0x930c8811);
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pci_write_config32(dev, 0x88, 0x24000d30);
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pci_write_config32(dev, 0xf4, 0x80408588);
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pci_write_config32(dev, 0xf4, 0x80808588);
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pci_write_config32(dev, 0xf4, 0x00808588);
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pci_write_config32(dev, 0xfc, 0x205b1708);
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#endif
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER;
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//reg32 |= PCI_COMMAND_SERR;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* For others, done in MRC. */
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#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)
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struct resource *res;
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u8 access_cntl;
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access_cntl = pci_read_config8(dev, 0x80);
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/* Enable writes to protected registers. */
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pci_write_config8(dev, 0x80, access_cntl | 1);
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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/* Number of ports and companion controllers. */
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reg32 = read32((void *)(uintptr_t)(res->base + 4));
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write32((void *)(uintptr_t)(res->base + 4),
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(reg32 & 0xfff00000) | 3);
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}
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/* Restore protection. */
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pci_write_config8(dev, 0x80, access_cntl);
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#endif
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printk(BIOS_DEBUG, "done.\n");
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}
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static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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u8 access_cntl;
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access_cntl = pci_read_config8(dev, 0x80);
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/* Enable writes to protected registers. */
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pci_write_config8(dev, 0x80, access_cntl | 1);
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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/* Restore protection. */
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pci_write_config8(dev, 0x80, access_cntl);
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = &usb_ehci_set_subsystem,
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};
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static struct device_operations usb_ehci_ops = {
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.read_resources = pci_ehci_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = usb_ehci_init,
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.scan_bus = 0,
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.ops_pci = &lops_pci,
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};
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static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d,
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0 };
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static const struct pci_driver pch_usb_ehci __pci_driver = {
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.ops = &usb_ehci_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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