312fc96874
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM registers on ICH5. Add ICH5 and i865 to the supported chips list. Enable the dumping of BAR6 on i865. Sample output: Disabling memory access: $ sudo setpci -s 6.0 0x04.b=0x0 $ sudo ./inteltool -m | head -n 9 Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7 Intel Northbridge: 8086:2570 (i865) Intel Southbridge: 8086:24d0 (ICH5) ============= MCHBAR ============ Access to BAR6 is currently disabled, attempting to enable. Enabled successfully. BAR6 = 0xfecf0000 (MEM) Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Joseph Smith <joe@settoplinux.org> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
145 lines
4.4 KiB
C
145 lines
4.4 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include "inteltool.h"
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/*
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* (G)MCH MMIO Config Space
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*/
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int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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{
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int i, size = (16 * 1024);
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volatile uint8_t *mchbar;
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uint64_t mchbar_phys;
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struct pci_dev *nb_device6; /* "overflow device" on i865 */
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uint16_t pcicmd6;
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printf("\n============= MCHBAR ============\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82865:
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/*
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* On i865, the memory access enable/disable bit (MCHBAREN on
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* i945/i965) is not in the MCHBAR (i945/i965) register but in
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* the PCICMD6 register. BAR6 and PCICMD6 reside on device 6.
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*
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* The actual base address is in BAR6 on i865 where on
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* i945/i965 the base address is in MCHBAR.
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*/
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nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0); /* Device 6 */
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mchbar_phys = pci_read_long(nb_device6, 0x10); /* BAR6 */
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pcicmd6 = pci_read_long(nb_device6, 0x04); /* PCICMD6 */
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/* Try to enable Memory Access Enable (MAE). */
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if (!(pcicmd6 & (1 << 1))) {
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printf("Access to BAR6 is currently disabled, "
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"attempting to enable.\n");
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pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1));
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if (pci_read_long(nb_device6, 0x04) & (1 << 1))
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printf("Enabled successfully.\n");
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else
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printf("Enable FAILED!\n");
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}
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mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */
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break;
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case PCI_DEVICE_ID_INTEL_82915:
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case PCI_DEVICE_ID_INTEL_82945GM:
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case PCI_DEVICE_ID_INTEL_82945GSE:
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case PCI_DEVICE_ID_INTEL_82945P:
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case PCI_DEVICE_ID_INTEL_82975X:
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mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_Q965:
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case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
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case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
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mchbar_phys = pci_read_long(nb, 0x48);
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/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
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* If it isn't, try to set it. This may fail, because there is
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* some bit that locks that bit, and isn't in the public
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* datasheets.
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*/
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if(!(mchbar_phys & 1))
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{
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printf("Access to the MCHBAR is currently disabled, "\
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"attempting to enable.\n");
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mchbar_phys |= 0x1;
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pci_write_long(nb, 0x48, mchbar_phys);
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if(pci_read_long(nb, 0x48) & 1)
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printf("Enabled successfully.\n");
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else
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printf("Enable FAILED!\n");
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}
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mchbar_phys &= 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82443LX:
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case PCI_DEVICE_ID_INTEL_82443BX:
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810E_MC:
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case PCI_DEVICE_ID_INTEL_82810DC:
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case PCI_DEVICE_ID_INTEL_82830M:
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printf("This northbridge does not have MCHBAR.\n");
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return 1;
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case PCI_DEVICE_ID_INTEL_GS45:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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default:
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printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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mchbar = map_physical(mchbar_phys, size);
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if (mchbar == NULL) {
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if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
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perror("Error mapping BAR6");
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else
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perror("Error mapping MCHBAR");
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exit(1);
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}
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if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
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printf("BAR6 = 0x%08llx (MEM)\n\n", mchbar_phys);
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else
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printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys);
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(mchbar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i));
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}
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unmap_physical((void *)mchbar, size);
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return 0;
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}
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