ee4bfbf3e1
This improves firmware boot time substantially. Because cbmem isn't available yet, we need to allocate some space in sram for the ttb. Doing cache initialization in the bootblock means we can implement this once per CPU instead of once per mainboard. Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65938 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73) exynos5420: flush caches and disable MMU in resume path This patch flushes the caches and disables the MMU before resuming. c32b9b3 ("Set up caching in the bootblock.") had a bug where the dcache and MMU remained enabled in the resume path. This caused the machine to hang on resume. However, other bugs were preventing us from testing this properly earlier on so it went unnoticed until now. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e Reviewed-on: https://chromium-review.googlesource.com/67007 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d) Squashed two related commits. Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6511 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
102 lines
2.1 KiB
Plaintext
102 lines
2.1 KiB
Plaintext
config CPU_SAMSUNG_EXYNOS5250
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select ARCH_BOOTBLOCK_ARMV7
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select ARCH_ROMSTAGE_ARMV7
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select ARCH_RAMSTAGE_ARMV7
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select HAVE_MONOTONIC_TIMER
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select HAVE_UART_SPECIAL
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select DYNAMIC_CBMEM
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bool
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default n
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if CPU_SAMSUNG_EXYNOS5250
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config BOOTBLOCK_CPU_INIT
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string
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default "cpu/samsung/exynos5250/bootblock.c"
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help
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CPU/SoC-specific bootblock code. This is useful if the
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bootblock must load microcode or copy data from ROM before
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searching for the bootblock.
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# ROM image layout.
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#
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# 0x0000: vendor-provided BL1 (8k).
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# 0x2000: bootblock
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# 0x2010-0x2090: reserved for CBFS master header.
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# 0xA000: Free for CBFS data.
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config BOOTBLOCK_ROM_OFFSET
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hex
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default 0x2000
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x2010
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config CBFS_ROM_OFFSET
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# Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
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hex "offset of CBFS data in ROM"
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default 0x0A000
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# Example SRAM/iRAM map for Exynos5250 platform:
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#
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# 0x0202_0000: vendor-provided BL1
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# 0x0202_3400: bootblock, assume up to 32KB in size
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# 0x0203_0000: romstage, assume up to 128KB in size.
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# 0x0207_8000: stack pointer
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config BOOTBLOCK_BASE
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hex
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default 0x02023400
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config ROMSTAGE_BASE
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hex
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default 0x02030000
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config ROMSTAGE_SIZE
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hex
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default 0x10000
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# Stack may reside in either IRAM or DRAM. We will define it to live
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# at the top of IRAM for now.
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#
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# Stack grows downward, push operation stores register contents in
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# consecutive memory locations ending just below SP
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config STACK_TOP
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hex
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default 0x02078000
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config STACK_BOTTOM
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hex
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default 0x02074000
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config STACK_SIZE
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hex
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default 0x4000
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# TODO We may probably move this to board-specific implementation files instead
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# of KConfig values.
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config CBFS_CACHE_ADDRESS
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hex "memory address to put CBFS cache data"
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default 0x0205c000
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config CBFS_CACHE_SIZE
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hex "size of CBFS cache data"
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default 0x00018000
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# TTB needs to be aligned to 16KB.
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config TTB_BUFFER
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hex "memory address of the TTB buffer"
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default 0x02058000
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config TTB_SIZE
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hex "size of the TTB buffer"
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default 0x4000
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config SYS_SDRAM_BASE
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hex
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default 0x40000000
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endif
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