ee73594575
List of changes: 1. Select FSP_HEADER_PATH 2. Select FSP_FD_PATH 3. Select PLATFORM_USES_FSP2_2 4. Select UDK_202005_BINDING Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
143 lines
2.8 KiB
Plaintext
143 lines
2.8 KiB
Plaintext
config SOC_INTEL_ALDERLAKE
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bool
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help
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Intel Alderlake support
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if SOC_INTEL_ALDERLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select IDT_IN_EVERY_STAGE
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select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
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select MICROCODE_BLOB_UNDISCLOSED
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select PLATFORM_USES_FSP2_2
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_MONOTONIC_TIMER
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select UDELAY_TSC
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select UDK_202005_BINDING
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config DCACHE_RAM_BASE
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default 0xfef00000
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config DCACHE_RAM_SIZE
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default 0x80000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x40400
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages. In the case of FSP_USES_CB_STACK default value will be
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sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement
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(~1KiB).
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config FSP_TEMP_RAM_SIZE
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hex
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default 0x20000
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help
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The amount of anticipated heap usage in CAR by FSP.
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Refer to Platform FSP integration guide document to know
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the exact FSP requirement for Heap setup.
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config IFD_CHIPSET
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string
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default "adl"
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config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x10000
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config PCR_BASE_ADDRESS
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hex
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default 0xfd000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config MMCONF_BASE_ADDRESS
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hex
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default 0xc0000000
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config CPU_BCLK_MHZ
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int
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default 100
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config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
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int
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default 120
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 133
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config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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int
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default 7
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config SOC_INTEL_I2C_DEV_MAX
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int
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default 6
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config SOC_INTEL_UART_DEV_MAX
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int
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default 7
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config CONSOLE_UART_BASE_ADDRESS
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hex
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default 0xfe032000
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depends on INTEL_LPSS_UART_FOR_CONSOLE
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# Clock divider parameters for 115200 baud rate
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# Baudrate = (UART source clcok * M) /(N *16)
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# ADL UART source clock: 120MHz
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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default 0x25a
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config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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default 0x7fff
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0xC000
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config CBFS_SIZE
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hex
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default 0x200000
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0x1400
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config FSP_HEADER_PATH
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string "Location of FSP headers"
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default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
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config FSP_FD_PATH
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string
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depends on FSP_USE_REPO
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default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd"
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endif
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