ef03afa405
Creator: Yinghai Lu <yhlu@tyan.com> AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
135 lines
2.9 KiB
C
135 lines
2.9 KiB
C
#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "pc80/mc146818rtc_early.c"
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#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
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#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
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#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
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#define SUPERIO_GPIO_IO_BASE 0x400
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static void sio_setup(void)
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{
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unsigned value;
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uint32_t dword;
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uint8_t byte;
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
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byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
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byte |= 0x20;
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pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
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dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
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dword |= (1<<29)|(1<<0);
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
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#if 1
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lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
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value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
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value &= 0xbf;
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
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#endif
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}
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#if CONFIG_LOGICAL_CPUS==1
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#include "cpu/amd/dualcore/dualcore_id.c"
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#else
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#include "cpu/amd/model_fxx/node_id.c"
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#endif
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static unsigned long main(unsigned long bist)
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{
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#if CONFIG_LOGICAL_CPUS==1
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struct node_core_id id;
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#else
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unsigned nodeid;
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#endif
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/* Make cerain my local apic is useable */
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// enable_lapic();
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#if CONFIG_LOGICAL_CPUS==1
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id = get_node_core_id_x();
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/* Is this a cpu only reset? */
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if (cpu_init_detected(id.nodeid)) {
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#else
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nodeid = get_node_id();
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/* Is this a cpu only reset? */
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if (cpu_init_detected(nodeid)) {
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#endif
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if (last_boot_normal()) {
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goto normal_image;
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} else {
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goto cpu_reset;
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}
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}
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/* Is this a secondary cpu? */
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if (!boot_cpu()) {
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if (last_boot_normal()) {
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goto normal_image;
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} else {
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goto fallback_image;
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}
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}
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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sio_setup();
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/* Setup the ck804 */
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ck804_enable_rom();
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/* Is this a deliberate reset by the bios */
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if (bios_reset_detected() && last_boot_normal()) {
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goto normal_image;
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}
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/* This is the primary cpu how should I boot? */
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else if (do_normal_boot()) {
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goto normal_image;
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}
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else {
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goto fallback_image;
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}
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normal_image:
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asm volatile ("jmp __normal_image"
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: /* outputs */
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: "a" (bist) /* inputs */
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: /* clobbers */
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);
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cpu_reset:
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#if 0
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//CPU reset will reset memtroller ???
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asm volatile ("jmp __cpu_reset"
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: /* outputs */
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: "a"(bist) /* inputs */
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: /* clobbers */
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);
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#endif
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fallback_image:
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return bist;
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}
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