Marc Jones ef6b08cc48 Add PCIe port disable debug message ...

The PCIe device enable function prints when it disables a device.
The PCIe ports(bridges) use a different routine that didn't print
the message. Add it to be consistent and to provide better debug
output.

Change-Id: I8462c48e7f4930db68703f0bfb710c01c9643a98
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1326
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)

2012-07-24 21:40:44 +02:00

..

arch/x86

Add standard header to prevent multiple inclusion

2012-07-24 08:37:22 +02:00

boot

Hook up MRC cache update

2012-05-11 00:30:03 +02:00

console

Add uartmem_init prototype.

2012-07-24 12:17:21 +02:00

cpu

Make MAX_PHYSICAL_CPUS invisible on non-AMD boards

2012-07-24 21:31:28 +02:00

devices

Simplify VGA card discovery

2012-07-22 13:10:44 +02:00

drivers

SPI flash layer: remove unused function spi_flash_free()

2012-07-24 02:37:39 +02:00

ec

Add EC component for SMSC MEC1308/1310

2012-04-02 18:42:40 +02:00

include

Add support for HM70 and NM70 LPC bridge

2012-07-24 12:26:26 +02:00

lib

Shrink the stack sizes we need in coreboot

2012-07-24 19:52:53 +02:00

mainboard

Drop (empty) sandybridge_late_initialization()

2012-07-24 15:54:43 +02:00

northbridge

Make ACPI code detect Sandy/Ivy Bridge dynamically

2012-07-24 19:53:13 +02:00

southbridge

Add PCIe port disable debug message

2012-07-24 21:40:44 +02:00

superio

servengines/pilot superio: add attribute unused

2012-07-09 12:36:02 +02:00

vendorcode

Move GGL0001 ACPI code to generic ChromeOS code

2012-07-24 08:36:03 +02:00

Kconfig

Add an option for Waiting for gdb connection if the gdb stub configuration is chosen.

2012-06-23 07:50:07 +02:00

Kconfig.deprecated_options

Unify ID_SECTION_OFFSET and mark it deprecated

2012-01-18 11:21:39 +01:00