ef6cb094b8
cause problems with certain toolchains. This patch will also safe some hard disk space for those of us working on laptops or netbooks with always too small disks. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
215 lines
6.7 KiB
Plaintext
215 lines
6.7 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 AMD
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## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
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## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_PAYLOAD = 1
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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default XIP_ROM_SIZE = 65536
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default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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arch i386 end
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driver mainboard.o
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if HAVE_ACPI_TABLES
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object acpi_tables.o
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object fadt.o
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makerule dsdt.c
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depends "$(MAINBOARD)/dsdt.asl"
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action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
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action "mv dsdt.hex dsdt.c"
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end
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object ./dsdt.o
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end
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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# object reset.o
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./cache_as_ram_auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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else
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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end
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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mainboardinit southbridge/via/k8t890/romstrap.inc
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ldscript /southbridge/via/k8t890/romstrap.lds
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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if USE_DCACHE_RAM
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mainboardinit cpu/amd/car/cache_as_ram.inc
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end
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if USE_FALLBACK_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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end
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end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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initobject cache_as_ram_auto.o
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else
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mainboardinit ./cache_as_ram_auto.inc
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end
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end
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if CONFIG_CHIP_NAME
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config chip.h
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end
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chip northbridge/amd/amdk8/root_complex # Root complex
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device apic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_939 # CPU
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8 # mc0
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device pci 18.0 on # Northbridge
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# Devices on link 0, link 0 == LDT 0
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chip southbridge/via/vt8237r # Southbridge
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register "ide0_enable" = "1" # Enable IDE channel 0
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register "ide1_enable" = "1" # Enable IDE channel 1
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register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
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register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
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register "fn_ctrl_lo" = "0" # Enable SB functions
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register "fn_ctrl_hi" = "0xad" # Enable SB functions
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device pci 0.0 on end # HT
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device pci f.1 on end # IDE
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device pci 11.0 on # LPC
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chip drivers/generic/generic # DIMM 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic # DIMM 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic # DIMM 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic # DIMM 0-1-1
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device i2c 53 on end
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end
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chip superio/winbond/w83627ehg # Super I/O
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2 (N/A on this board)
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 off # PS/2 keyboard (off)
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end
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device pnp 2e.106 off # Serial flash
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io 0x60 = 0x100
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end
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device pnp 2e.007 off # GPIO 1
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end
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device pnp 2e.107 on # Game port
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io 0x60 = 0x201
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end
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device pnp 2e.207 on # MIDI
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io 0x62 = 0x330
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irq 0x70 = 0xa
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end
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device pnp 2e.307 off # GPIO 6
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end
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device pnp 2e.8 off # WDTO_PLED
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end
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device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup
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end
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device pnp 2e.109 off # GPIO 3
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end
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device pnp 2e.209 off # GPIO 4
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end
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device pnp 2e.309 on # GPIO5
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end
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device pnp 2e.a off # ACPI
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end
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device pnp 2e.b on # Hardware monitor
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io 0x60 = 0x290
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irq 0x70 = 0
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end
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end
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end
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device pci 12.0 off end # VIA LAN (off, other chip used)
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end
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chip southbridge/via/k8t890 # "Southbridge" K8T890
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end
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end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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end
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end
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