ef8deaffcb
This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
47 lines
1.5 KiB
Plaintext
47 lines
1.5 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* NOTE: The layout of the GNVS structure below must match the layout in
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* soc/intel/apollolake/include/soc/nvs.h !!!
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*
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*/
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External (NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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PCNT, 8, // 0x00 - Processor Count
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PPCM, 8, // 0x01 - Max PPC State
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LIDS, 8, // 0x02 - LID State
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PWRS, 8, // 0x03 - AC Power State
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DPTE, 8, // 0x04 - Enable DPTF
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CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console
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PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
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GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
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NHLA, 64, // 0x19 - 0x20 - NHLT Address
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NHLL, 32, // 0x21 - 0x24 - NHLT Length
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PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
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/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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}
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