ef8deaffcb
This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
125 lines
3.8 KiB
C
125 lines
3.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_APOLLOLAKE_CHIP_H_
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#define _SOC_APOLLOLAKE_CHIP_H_
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#include <soc/gpe.h>
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#include <soc/gpio_defs.h>
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#include <soc/gpio.h>
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#include <soc/intel/common/lpss_i2c.h>
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#include <device/i2c.h>
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#include <soc/pm.h>
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#define CLKREQ_DISABLED 0xf
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#define APOLLOLAKE_I2C_DEV_MAX 8
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struct apollolake_i2c_config {
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/* Bus should be enabled prior to ramstage with temporary base */
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int early_init;
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/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
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enum i2c_speed speed;
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/* Specific bus speed configuration */
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struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT];
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};
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/* Serial IRQ control. SERIRQ_QUIET is the default (0). */
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enum serirq_mode {
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SERIRQ_QUIET,
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SERIRQ_CONTINUOUS,
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SERIRQ_OFF,
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};
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struct soc_intel_apollolake_config {
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/*
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* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
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* four CLKREQ inputs, but six root ports. Root ports without an
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* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
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*/
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uint8_t pcie_rp0_clkreq_pin;
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uint8_t pcie_rp1_clkreq_pin;
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uint8_t pcie_rp2_clkreq_pin;
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uint8_t pcie_rp3_clkreq_pin;
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uint8_t pcie_rp4_clkreq_pin;
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uint8_t pcie_rp5_clkreq_pin;
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/* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
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*/
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uint32_t emmc_tx_cmd_cntl;
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/* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
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*/
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uint32_t emmc_tx_data_cntl1;
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/* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
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* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
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* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec.
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*/
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uint32_t emmc_tx_data_cntl2;
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/* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
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* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
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* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec.
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*/
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uint32_t emmc_rx_cmd_data_cntl1;
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/* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
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* [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
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*/
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uint32_t emmc_rx_strobe_cntl;
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/* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
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*/
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uint32_t emmc_rx_cmd_data_cntl2;
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/* Configure serial IRQ (SERIRQ) line. */
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enum serirq_mode serirq_mode;
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/* I2C bus configuration */
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struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX];
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uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
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uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
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uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */
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/* Configure LPSS S0ix Enable */
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uint8_t lpss_s0ix_enable;
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/* Enable DPTF support */
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int dptf_enable;
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/* Configure Audio clk gate and power gate
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* IOSF-SB port ID 92 offset 0x530 [5] and [3]
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*/
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uint8_t hdaudio_clk_gate_enable;
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uint8_t hdaudio_pwr_gate_enable;
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uint8_t hdaudio_bios_config_lockdown;
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/* SLP S3 minimum assertion width. */
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int slp_s3_assertion_width_usecs;
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/* GPIO pin for PERST_0 */
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uint16_t prt0_gpio;
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};
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#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
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