efcee767de
Non-x86 boards currently need to hardcode the position of their CBFS master header in a Kconfig. This is very brittle because it is usually put in between the bootblock and the first CBFS entry, without any checks to guarantee that it won't overlap either of those. It is not fun to debug random failures that move and disappear with tiny alignment changes because someone decided to write "ORBC1112" over some part of your data section (in a way that is not visible in the symbolized .elf binaries, only in the final image). This patch seeks to prevent those issues and reduce the need for manual configuration by making the image layout a completely automated part of cbfstool. Since automated placement of the CBFS header means we can no longer hardcode its position into coreboot, this patch takes the existing x86 solution of placing a pointer to the header at the very end of the CBFS-managed section of the ROM and generalizes it to all architectures. This is now even possible with the read-only/read-write split in ChromeOS, since coreboot knows how large that section is from the CBFS_SIZE Kconfig (which is by default equal to ROM_SIZE, but can be changed on systems that place other data next to coreboot/CBFS in ROM). Also adds a feature to cbfstool that makes the -B (bootblock file name) argument on image creation optional, since we have recently found valid use cases for CBFS images that are not the first boot medium of the device (instead opened by an earlier bootloader that can already interpret CBFS) and therefore don't really need a bootblock. BRANCH=None BUG=None TEST=Built and booted on Veyron_Pinky, Nyan_Blaze and Falco. Change-Id: Ib715bb8db258e602991b34f994750a2d3e2d5adf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9879c0fbd57f105254c54bacb3e592acdcad35c Original-Change-Id: Ifcc755326832755cfbccd6f0a12104cba28a20af Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229975 Reviewed-on: http://review.coreboot.org/9620 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
62 lines
1.4 KiB
Plaintext
62 lines
1.4 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 Google Inc.
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##
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## This software is licensed under the terms of the GNU General Public
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## License version 2, as published by the Free Software Foundation, and
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## may be copied, distributed, and modified under those terms.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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# To execute, do:
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# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
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if BOARD_EMULATION_QEMU_UCB_RISCV
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SOC_UCB_RISCV
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select BOARD_ROMSIZE_KB_4096
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select ARCH_BOOTBLOCK_RISCV
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select HAVE_UART_SPECIAL
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config MAINBOARD_DIR
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string
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default emulation/qemu-riscv
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config MAINBOARD_PART_NUMBER
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string
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default "QEMU RISCV"
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config MAX_CPUS
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int
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default 1
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config MAINBOARD_VENDOR
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string
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default "UCB"
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config DRAM_SIZE_MB
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int
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default 32768
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# Memory map for qemu riscv
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#
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# 0x0000_0000: jump instruction (by qemu)
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# 0x0002_0000: bootblock (entry of kernel / firmware)
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# 0x0003_0000: romstage, assume up to 128KB in size.
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# 0x0007_ff00: stack pointer
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# 0x0010_0000: CBFS header
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# 0x0011_0000: CBFS data
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# 0x0100_0000: reserved for ramstage
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config RAMTOP
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hex
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default 0x1000000
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endif # BOARD_EMULATION_QEMU_UCB_RISCV
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