efddcfbb52
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over the bootblock, then exits to the romstage. this is necessary for some SOC (e.g. tegra124) which runs the bootblock on a different architecture. With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock. Then, the bootblock loads the romstage over the verstage and exits to the romstage. this is probably necessary for some SOC (e.g. rockchip) which does not have SRAM big enough to fit the verstage and the romstage at the same time. BUG=none TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544 Original-Reviewed-on: https://chromium-review.googlesource.com/212365 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Note: This purposefully is probably broken in vendorcode/google/chromeos as I'm just trying to set a base for dropping more patches in. The vboot paths will have to change from how they are currently constructed. (cherry picked from commit 4fa17395113d86445660091413ecb005485f8014) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9 Reviewed-on: http://review.coreboot.org/8881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
145 lines
3.3 KiB
Plaintext
145 lines
3.3 KiB
Plaintext
config SOC_NVIDIA_TEGRA124
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bool
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default n
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select ARCH_BOOTBLOCK_ARMV4
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select ARCH_VERSTAGE_ARMV4
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select ARCH_ROMSTAGE_ARMV7
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select ARCH_RAMSTAGE_ARMV7
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select HAVE_UART_SPECIAL
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select BOOTBLOCK_CONSOLE
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select ARM_BOOTBLOCK_CUSTOM
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select ARM_LPAE
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if SOC_NVIDIA_TEGRA124
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/nvidia/tegra124/bootblock.c"
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help
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CPU/SoC-specific bootblock code. This is useful if the
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bootblock must load microcode or copy data from ROM before
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searching for the bootblock.
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# ROM image layout.
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#
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# 0x00000 Combined bootblock and BCT blob
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# 0x18000 Master CBFS header.
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# 0x18080 Free for CBFS data.
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#
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# iRAM (256k) layout.
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# (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
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# so the bootblock loading address must be placed after that. After the
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# handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
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#
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# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
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# 0x4000_4020 CBFS mapping cache (96K-32B)
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# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
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# 0x4002_0000 Bootblock (max 48KB).
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# 0x4002_C000 ROM stage (max 80KB).
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# 0x4003_FFFF End of iRAM.
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#
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# if VBOOT2_VERIFY_FIRMWARE,
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# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
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# 0x4000_4020 CBMEM console area (8K-32B)
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# 0x4000_6000 CBFS mapping cache (72K)
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# 0x4001_8000 vboot work buffer (16K)
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# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
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# 0x4002_0000 bootblock and romstage (max 70KB).
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# 0x4003_1000 verstage (max 60KB).
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# 0x4003_FFFF End of iRAM.
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config BOOTBLOCK_ROM_OFFSET
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hex
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default 0x0
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x18000
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config CBFS_ROM_OFFSET
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hex "offset of CBFS data in ROM"
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default 0x18080
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config SYS_SDRAM_BASE
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hex
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default 0x80000000
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config BOOTBLOCK_BASE
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hex
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default 0x40020000
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# this has to be big enough to leave room big enough for the larger of the
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# bootblock and the romstage.
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config VERSTAGE_BASE
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hex
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default 0x40031000
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# with vboot2, romstage is loaded over to the bootblock space
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config ROMSTAGE_BASE
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hex
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default 0x40020000 if VBOOT2_VERIFY_FIRMWARE
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default 0x4002c000
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config RAMSTAGE_BASE
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hex
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default 0x80200000
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config STACK_TOP
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hex
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default 0x40020000
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config STACK_BOTTOM
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hex
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default 0x4001c000
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# This is the ramstage thread stack, *not* the same as above! Currently unused.
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config STACK_SIZE
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hex
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default 0x800
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# TTB needs to be aligned to 16KB. Stick it in iRAM.
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config TTB_BUFFER
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hex "memory address of the TTB buffer"
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default 0x40000000
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config CBFS_CACHE_ADDRESS
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hex "memory address to put CBFS cache data"
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default 0x40004020
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config CBFS_CACHE_SIZE
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hex "size of CBFS cache data"
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default 0x00012000 if VBOOT2_VERIFY_FIRMWARE
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default 0x00016000
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config VBOOT_WORK_BUFFER_ADDRESS
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hex "memory address of vboot work buffer"
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default 0x40018000
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config VBOOT_WORK_BUFFER_SIZE
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hex "size of vboot work buffer"
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default 0x00004000
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config TEGRA124_MODEL_TD570D
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bool "TD570D"
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config TEGRA124_MODEL_TD580D
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bool "TD580D"
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config TEGRA124_MODEL_CD570M
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bool "CD570M"
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config TEGRA124_MODEL_CD580M
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bool "CD580M"
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# Default to 2GHz, the lowest maximum frequency.
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config PLLX_KHZ
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int
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default 2000000 if TEGRA124_MODEL_TD570D
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default 2300000 if TEGRA124_MODEL_TD580D
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default 2100000 if TEGRA124_MODEL_CD570M
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default 2300000 if TEGRA124_MODEL_CD580M
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default 2000000
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endif
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