d8740c31df
For multiple sockets platform 16 may not be enough, so increase it to 32. Tested=On a platform that has more than 16 memory DIMM, SMBIOS type 17 can show all DIMM tables. Change-Id: If72a8622ac1e7e67646aa4dd24b99637fb8b1297 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: lichenchen.carl <lichenchen.carl@bytedance.com>
120 lines
2.7 KiB
C
120 lines
2.7 KiB
C
/* Memory information */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _MEMORY_INFO_H_
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#define _MEMORY_INFO_H_
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#include <stdint.h>
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#define DIMM_INFO_SERIAL_SIZE 4
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#define DIMM_INFO_PART_NUMBER_SIZE 33
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#define DIMM_INFO_TOTAL 32
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/**
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* If this table is filled and put in CBMEM,
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* then these info in CBMEM will be used to generate smbios type 17 table
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*
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* Values are specified according to the JEDEC SPD Standard.
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*/
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struct dimm_info {
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/*
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* Size of the module in MiB.
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*/
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uint32_t dimm_size;
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/*
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* SMBIOS (not SPD) device type.
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*
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* See the smbios.h smbios_memory_type enum.
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*/
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uint16_t ddr_type;
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/*
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* ddr_frequency is deprecated.
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* Use max_speed_mts and configured_speed_mts instead.
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*/
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uint16_t ddr_frequency;
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uint8_t rank_per_dimm;
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uint8_t channel_num;
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uint8_t dimm_num;
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uint8_t bank_locator;
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/*
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* SPD serial number.
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*/
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uint8_t serial[DIMM_INFO_SERIAL_SIZE];
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/*
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* The last byte is '\0' for the end of string
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*
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* Must contain only printable ASCII.
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*/
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uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE];
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/*
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* SPD Manufacturer ID
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*/
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uint16_t mod_id;
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/*
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* SPD Module Type.
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*
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* See spd.h for valid values.
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*
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* e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
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*/
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uint8_t mod_type;
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/*
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* SPD bus width.
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*
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* Bits 0 - 2 encode the primary bus width:
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* 0b000 = 8 bit width
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* 0b001 = 16 bit width
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* 0b010 = 32 bit width
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* 0b011 = 64 bit width
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*
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* Bits 3 - 4 encode the extension bits (ECC):
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* 0b00 = 0 extension bits
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* 0b01 = 8 bit of ECC
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*
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* e.g.,
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* 64 bit bus with 8 bits of ECC (72 bits total): 0b1011
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* 64 bit bus with 0 bits of ECC (64 bits total): 0b0011
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*
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* See the smbios.h smbios_memory_bus_width enum.
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*/
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uint8_t bus_width;
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/*
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* Voltage Level
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*/
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uint16_t vdd_voltage;
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/*
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* Max speed in MT/s
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* If the value is 0, ddr_frequency should be used instead.
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*/
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uint16_t max_speed_mts;
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/*
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* Configured speed in MT/s
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* If the value is 0, ddr_frequency should be used instead.
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*/
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uint16_t configured_speed_mts;
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} __packed;
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struct memory_info {
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/*
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* SMBIOS error correction type.
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* See the smbios.h smbios_memory_array_ecc enum.
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*/
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uint8_t ecc_type;
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/* Maximum capacity the DRAM controller/mainboard supports */
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uint32_t max_capacity_mib;
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/* Maximum number of DIMMs the DRAM controller/mainboard supports */
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uint16_t number_of_devices;
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/* active DIMM configuration */
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uint8_t dimm_cnt;
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struct dimm_info dimm[DIMM_INFO_TOTAL];
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} __packed;
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/*
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* mainboard_get_dram_part_num returns a DRAM part number override string
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* return NULL = no part number override provided by mainboard
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* return non-NULL = pointer to a string terminating in '\0'
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*/
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const char *mainboard_get_dram_part_num(void);
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#endif
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