f17f647a62
Fix configuration of all boards. (Abuild tested) Hopefully fix compilation of PPC boards (they've never compiled for me.) Apologize profusely. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
113 lines
3.0 KiB
Plaintext
113 lines
3.0 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses HAVE_MP_TABLE
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uses CONFIG_CBFS
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_PAYLOAD
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_SMP
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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default ROM_SIZE = 256 * 1024
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default HAVE_FALLBACK_BOOT = 1
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default HAVE_MP_TABLE = 1
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default HAVE_HARD_RESET = 0
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default HAVE_PIRQ_TABLE = 1
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default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
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default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
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default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
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default ROM_IMAGE_SIZE = 64 * 1024
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default FALLBACK_SIZE = 128 * 1024
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default STACK_SIZE = 8 * 1024
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default HEAP_SIZE = 16 * 1024
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default HAVE_OPTION_TABLE = 0
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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default CONFIG_SMP = 1
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default CONFIG_MAX_CPUS = 2
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default CONFIG_IOAPIC = 1
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default CROSS_COMPILE = ""
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default CC = "$(CROSS_COMPILE)gcc -m32"
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default HOSTCC = "gcc"
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default CONFIG_CONSOLE_SERIAL8250 = 1
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default TTYS0_BAUD = 115200
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default TTYS0_BASE = 0x3f8
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default TTYS0_LCS = 0x3 # 8n1
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default DEFAULT_CONSOLE_LOGLEVEL = 9
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default MAXIMUM_CONSOLE_LOGLEVEL = 9
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default CONFIG_CONSOLE_VGA = 1
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default CONFIG_PCI_ROM_RUN = 1
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#
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# CBFS
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#
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#
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default CONFIG_CBFS=0
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end
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