f1b58b7835
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <southbridge/amd/sb700/sb700.h>
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#include <southbridge/amd/sb700/smbus.h>
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#include <southbridge/amd/rs780/rs780.h>
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void set_pcie_dereset(void)
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{
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u8 byte;
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u16 word;
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struct device *sm_dev;
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/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
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/* set 0 to bit2 :disable GPM8 as AZ_RST output */
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byte = pm_ioread(0x8d);
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byte &= ~((1 << 1) | (1 << 2));
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pm_iowrite(0x8d, byte);
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/* set the GPM8 and GPM9 output enable and the value to 1 */
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byte = pm_ioread(0x94);
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byte &= ~((1 << 2) | (1 << 3));
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byte |= ((1 << 0) | (1 << 1));
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pm_iowrite(0x94, byte);
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/* set the GPIO65 output enable and the value is 1 */
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sm_dev = pcidev_on_root(0x14, 0);
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word = pci_read_config16(sm_dev, 0x7e);
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word |= (1 << 0);
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word &= ~(1 << 4);
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pci_write_config16(sm_dev, 0x7e, word);
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}
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void set_pcie_reset(void)
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{
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u8 byte;
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u16 word;
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struct device *sm_dev;
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/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
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/* set 0 to bit2 :disable GPM8 as AZ_RST output */
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byte = pm_ioread(0x8d);
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byte &= ~((1 << 1) | (1 << 2));
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pm_iowrite(0x8d, byte);
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/* set the GPM8 and GPM9 output enable and the value to 0 */
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byte = pm_ioread(0x94);
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byte &= ~((1 << 2) | (1 << 3));
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byte &= ~((1 << 0) | (1 << 1));
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pm_iowrite(0x94, byte);
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/* set the GPIO65 output enable and the value is 0 */
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sm_dev = pcidev_on_root(0x14, 0);
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word = pci_read_config16(sm_dev, 0x7e);
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word &= ~(1 << 0);
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word &= ~(1 << 4);
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pci_write_config16(sm_dev, 0x7e, word);
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}
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/*
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* justify the dev3 is exist or not
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* NOTE: This just copied from AMD Tilapia code.
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* It is completely unknown if it will work at all for this board.
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*/
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int is_dev3_present(void)
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{
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u16 word;
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struct device *sm_dev;
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/* access the smbus extended register */
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sm_dev = pcidev_on_root(0x14, 0);
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/* put the GPIO68 output to tristate */
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word = pci_read_config16(sm_dev, 0x7e);
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word |= 1 << 6;
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pci_write_config16(sm_dev, 0x7e,word);
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/* read the GPIO68 input status */
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word = pci_read_config16(sm_dev, 0x7e);
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return !(word & (1 << 10));
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}
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/*************************************************
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* enable the dedicated function in this board.
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* This function called early than rs780_enable.
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*************************************************/
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static void mainboard_enable(struct device *dev)
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{
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printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
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set_pcie_dereset();
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/* get_ide_dma66(); */
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/* set_thermal_config(); */
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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