f20c355a1f
This is a preparation to make the next patch result in identical images for timeless builds and also aligns Zork's DSDT more with Guybrush's DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46835b404be13f150c68680afb3fcc78639e08f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
55 lines
1.1 KiB
Plaintext
55 lines
1.1 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <variant/ec.h>
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/* DefinitionBlock Statement */
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#include <acpi/acpi.h>
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DefinitionBlock (
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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#include <acpi/dsdt_top.asl>
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Name(LIDS, 0)
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#include <globalnvs.asl>
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/* Power state notification to ALIB */
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#include <pnot.asl>
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/* Contains the supported sleep states for this chipset */
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#include <soc/amd/common/acpi/sleepstates.asl>
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/* Contains _SWS methods */
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#include <soc/amd/common/acpi/acpi_wake_source.asl>
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/* System Bus */
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Scope(\_SB) { /* Start \_SB scope */
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* Describe the SOC */
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#include <soc.asl>
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} /* End \_SB scope */
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/* Thermal handler */
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#include <variant/acpi/thermal.asl>
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/* ChromeOS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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}
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/* End of ASL file */
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