f23ae0b0f6
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2adf28d805fe248d55a9514f74c38280c0ad9a78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
27 lines
655 B
C
27 lines
655 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/* This file is part of the coreboot project. */
|
|
|
|
#ifndef _CPU_INTEL_COMMON_H
|
|
#define _CPU_INTEL_COMMON_H
|
|
|
|
#include <stdint.h>
|
|
|
|
void set_vmx_and_lock(void);
|
|
void set_feature_ctrl_vmx(void);
|
|
void set_feature_ctrl_lock(void);
|
|
|
|
/*
|
|
* Init CPPC block with MSRs for Intel Enhanced Speed Step Technology.
|
|
* Version 2 is suggested--this function's implementation of version 3
|
|
* may have room for improvment.
|
|
*/
|
|
struct cppc_config;
|
|
void cpu_init_cppc_config(struct cppc_config *config, u32 version);
|
|
|
|
/*
|
|
* Returns true if it's not thread 0 on a hyperthreading enabled core.
|
|
*/
|
|
bool intel_ht_sibling(void);
|
|
|
|
#endif
|