f300f36210
This driver uses an fmap region for the MRC cache instead of a CBFS file which makes it easier to manage if one wants to write protect it. Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
93 lines
2.2 KiB
Plaintext
93 lines
2.2 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config NORTHBRIDGE_INTEL_HASWELL
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bool
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select CPU_INTEL_HASWELL
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select CACHE_MRC_SETTINGS
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select INTEL_DDI
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select INTEL_GMA_ACPI
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select RELOCATABLE_RAMSTAGE
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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if NORTHBRIDGE_INTEL_HASWELL
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/intel/haswell/bootblock.c"
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config VGA_BIOS_ID
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string
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default "8086,0166"
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config CACHE_MRC_SIZE_KB
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int
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default 512
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config DCACHE_RAM_BASE
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hex
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default 0xff7c0000
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config DCACHE_RAM_SIZE
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hex
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default 0x10000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x30000
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help
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The amount of cache-as-ram region required by the reference code.
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config DCACHE_RAM_ROMSTAGE_STACK_SIZE
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hex
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default 0x2000
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help
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The amount of anticipated stack usage from the data cache
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during pre-ram ROM stage execution.
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config HAVE_MRC
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bool "Add a System Agent binary"
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help
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Select this option to add a System Agent binary to
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the resulting coreboot image.
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Note: Without this binary coreboot will not work
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config MRC_FILE
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string "Intel System Agent path and filename"
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depends on HAVE_MRC
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default "mrc.bin"
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help
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The path and filename of the file to use as System Agent
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binary.
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config PRE_GRAPHICS_DELAY
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int "Graphics initialization delay in ms"
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default 0
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help
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On some systems, coreboot boots so fast that connected monitors
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(mostly TVs) won't be able to wake up fast enough to talk to the
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VBIOS. On those systems we need to wait for a bit before executing
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the VBIOS.
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endif
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