Mario Scheithauer f343ed42eb mb/siemens/mc_ehl2: Set coreboot ready LED ...

This mainboard has its own coreboot ready LED. The LED is switched
on via GPIO GPP_F20.

Change-Id: I3570d691e90d2cb6e11b856b876f0327da118522
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

2021-10-14 13:05:54 +00:00

..

acpi

src/acpi to src/lib: Fix spelling errors

2021-10-05 18:06:39 +00:00

arch

arch/x86,cpu/x86: Introduce new method for accessing cpu_info

2021-10-05 22:38:45 +00:00

commonlib

src/acpi to src/lib: Fix spelling errors

2021-10-05 18:06:39 +00:00

console

src/acpi to src/lib: Fix spelling errors

2021-10-05 18:06:39 +00:00

cpu

soc/amd/cezanne,soc/intel/common: rework CPPC table generation

2021-10-13 13:51:24 +00:00

device

src/acpi to src/lib: Fix spelling errors

2021-10-05 18:06:39 +00:00

drivers

drivers/pc80/tpm: Fix wrong debug message

2021-10-13 13:57:05 +00:00

ec

ec/google/chromeec: Register USB-C mux operations

2021-10-06 22:20:32 +00:00

include

soc/amd/cezanne,soc/intel/common: rework CPPC table generation

2021-10-13 13:51:24 +00:00

lib

lib/thread: Remove thread stack alignment requirement

2021-10-05 22:40:25 +00:00

mainboard

mb/siemens/mc_ehl2: Set coreboot ready LED

2021-10-14 13:05:54 +00:00

northbridge

nb/intel/haswell: Add HDAU ACPI device

2021-10-13 17:47:01 +00:00

security

security/vboot: Remove vb2ex_hwcrypto stubs

2021-10-07 05:26:19 +00:00

soc

src/soc/amd/cezanne: enable clock gating

2021-10-13 22:01:52 +00:00

southbridge

sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1

2021-10-14 11:17:52 +00:00

superio

src/soc to src/superio: Fix spelling errors

2021-10-05 18:07:08 +00:00

vendorcode

vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne

2021-10-11 15:55:35 +00:00

Kconfig

lib/thread: Switch to using CPU_INFO_V2

2021-10-05 22:39:16 +00:00