system76-coreboot

Files

Siyuan Wang f3b86b3136 AMD agesa: add enable cache at the end of disable_cache_as_ram

add this code according to src/include/cpu/x86/cache.h ,line 92,
functin enable_cache()

Change-Id: Ida96a98397eeed98dd61ca979e8c5a33bf00f9e5
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1662
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

2012-11-02 21:04:28 +01:00

amd

AMD agesa: add enable cache at the end of disable_cache_as_ram

2012-11-02 21:04:28 +01:00

intel

Correct FSB reading in speedstep ACPI

2012-11-02 20:09:57 +01:00

via

VIA Nano: Add support for VIA Nano CPUs

2012-09-05 03:43:02 +02:00

x86

Synchronize rdtsc instructions