f3cce2f3c4
-- When building for UMA, reduce the limit for DRAM below 4GB from E0000000 to C0000000. This is needed to accomodate the UMA frame buffer. -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En and Tom2ForceMemTypeWB) are not set consistently across cores. -- Enable TOM2 only if DRAM is present above 4GB. -- Use AMD Tom2ForceMemTypeWB feature to avoid the need for variable MTRR ranges above 4GB. -- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for DRAM above 4GB. AMD systems use this option to conserve MTRRs. -- Northbridge.c change to deduct UMA memory from DRAM size reported by ram_resource. This corrects a problem where mtrr.c generates an unexpected variable MTRR range. -- Correct problem causing build failure when CONFIG_GFXUMA=1 and CONFIG_VAR_MTRR_HOLE=0. -- Reserve the UMA DRAM range for AMD K8 as is already done for AMD family 10h. Tested with mahogany on ECS A780G-GM with 2GB and 4GB. Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
83 lines
2.4 KiB
C
83 lines
2.4 KiB
C
#ifndef CPU_X86_MTRR_H
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#define CPU_X86_MTRR_H
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/* These are the region types */
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#define MTRR_TYPE_UNCACHEABLE 0
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#define MTRR_TYPE_WRCOMB 1
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/*#define MTRR_TYPE_ 2*/
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/*#define MTRR_TYPE_ 3*/
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#define MTRR_TYPE_WRTHROUGH 4
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#define MTRR_TYPE_WRPROT 5
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#define MTRR_TYPE_WRBACK 6
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#define MTRR_NUM_TYPES 7
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#define MTRRcap_MSR 0x0fe
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#define MTRRdefType_MSR 0x2ff
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#define MTRRdefTypeEn (1 << 11)
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#define MTRRdefTypeFixEn (1 << 10)
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#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
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#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
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#define NUM_FIXED_RANGES 88
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#define MTRRfix64K_00000_MSR 0x250
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#define MTRRfix16K_80000_MSR 0x258
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#define MTRRfix16K_A0000_MSR 0x259
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#define MTRRfix4K_C0000_MSR 0x268
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#define MTRRfix4K_C8000_MSR 0x269
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#define MTRRfix4K_D0000_MSR 0x26a
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#define MTRRfix4K_D8000_MSR 0x26b
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#define MTRRfix4K_E0000_MSR 0x26c
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#define MTRRfix4K_E8000_MSR 0x26d
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#define MTRRfix4K_F0000_MSR 0x26e
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#define MTRRfix4K_F8000_MSR 0x26f
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#if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
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#include <device/device.h>
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void enable_fixed_mtrr(void);
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void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
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void x86_setup_mtrrs(unsigned address_bits);
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int x86_mtrr_check(void);
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void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
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void x86_setup_fixed_mtrrs(void);
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#endif
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/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
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#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
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# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
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#endif
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#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
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# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
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#endif
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#if !defined(CONFIG_RAMTOP)
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# error "CONFIG_RAMTOP not defined"
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#endif
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#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
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# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
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#endif
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#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
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# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
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#endif
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#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
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# error "CONFIG_RAMTOP must be a power of 2"
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#endif
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#if !defined (ASSEMBLY)
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#if defined(CONFIG_XIP_ROM_SIZE)
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# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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extern unsigned long AUTO_XIP_ROM_BASE;
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# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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# else
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# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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# endif
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#endif
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#endif
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#endif /* CPU_X86_MTRR_H */
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