f3f36faf35
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
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*/
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#ifndef __SDRAMMODE_H_DEFINED
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#define __SDRAMMODE_H_DEFINED
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// SDRAM Mode Register definitions, per JESD79D
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// These are transmitted via A0-A13
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// Burst length
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#define SDRAM_BURST_2 (1<<0)
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#define SDRAM_BURST_4 (2<<0)
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#define SDRAM_BURST_8 (3<<0)
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#define SDRAM_BURST_SEQUENTIAL (0<<3)
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#define SDRAM_BURST_INTERLEAVED (1<<3)
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#define SDRAM_CAS_2_0 (2<<4)
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#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */
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#define SDRAM_CAS_1_5 (5<<4) /* Optional */
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#define SDRAM_CAS_2_5 (6<<4)
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#define SDRAM_CAS_MASK (7<<4)
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#define SDRAM_MODE_NORMAL (0 << 7)
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#define SDRAM_MODE_TEST (1 << 7)
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#define SDRAM_MODE_DLL_RESET (2 << 7)
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// Extended Mode Register
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#define SDRAM_EXTMODE_DLL_ENABLE (0 << 0)
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#define SDRAM_EXTMODE_DLL_DISABLE (1 << 0)
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#define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)
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#define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */
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#endif // __SDRAMMODE_H_DEFINED
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