f48acbda7b
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
26 lines
909 B
C
26 lines
909 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/bootblock.h>
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#include <device/pci_ops.h>
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#include "haswell.h"
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void bootblock_early_northbridge_init(void)
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{
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uint32_t reg;
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/*
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* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
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* because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent
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* non-explicit config accesses use MCFG. This code also assumes that
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* bootblock_northbridge_init() is the first thing called in the non-asm
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* boot block code. The final assumption is that no assembly code is using
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* the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
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*/
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reg = 0;
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pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg);
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reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
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pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
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}
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