f4d6e9085d
ltiming and clock_div are not support for MT8173, so we separate them to weak function: mtk_i2c_dump_more_info() Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I3228c6953be5fac18a76029702b878a34c7563f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58074 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
365 lines
9.2 KiB
C
365 lines
9.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/i2c_simple.h>
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#include <soc/pll.h>
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#include <soc/i2c.h>
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#include <soc/gpio.h>
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#include <timer.h>
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#define I2C_CLK_HZ (UNIVPLL_HZ / 20)
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struct mtk_i2c mtk_i2c_bus_controller[] = {
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[0] = {
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.i2c_regs = (void *)(I2C_BASE),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE),
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[1] = {
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.i2c_regs = (void *)(I2C_BASE + 0x1000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x180),
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[2] = {
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.i2c_regs = (void *)(I2C_BASE + 0x2000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x300),
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[3] = {
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.i2c_regs = (void *)(I2C_BASE + 0x3000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x400),
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[4] = {
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.i2c_regs = (void *)(I2C_BASE + 0x4000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480),
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[5] = {
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.i2c_regs = (void *)(I2C_BASE - 0x100000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x500),
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[6] = {
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.i2c_regs = (void *)(I2C_BASE - 0xFF000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580),
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[7] = {
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.i2c_regs = (void *)(I2C_BASE - 0xFE000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x600),
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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};
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#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller)
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struct pad_func {
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gpio_t gpio;
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u8 func;
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};
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#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func}
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static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
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[0] = {
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PAD_FUNC(SDA0, SDA0),
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PAD_FUNC(SCL0, SCL0),
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},
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[1] = {
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PAD_FUNC(SDA1, SDA1),
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PAD_FUNC(SCL1, SCL1),
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},
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[2] = {
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PAD_FUNC(SDA2, SDA2),
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PAD_FUNC(SCL2, SCL2),
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},
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[3] = {
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PAD_FUNC(SDA3, SDA3),
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PAD_FUNC(SCL3, SCL3),
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},
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[4] = {
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PAD_FUNC(SDA4, SDA4),
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PAD_FUNC(SCL4, SCL4),
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},
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[5] = {
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PAD_FUNC(HDMIRX_SCL, SCL5),
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PAD_FUNC(HDMIRX_SDA, SDA5),
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},
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[6] = {
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PAD_FUNC(HDMITX_SCL, SCL6),
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PAD_FUNC(HDMITX_SDA, SDA6),
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},
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[7] = {
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PAD_FUNC(HDMIRX_HTPLG, SCL7),
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PAD_FUNC(HDMIRX_PWR5V, SDA7),
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},
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};
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static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
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{
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assert(bus < I2C_BUS_NUMBER);
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const struct pad_func *ptr = i2c_funcs[bus];
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for (size_t i = 0; i < 2; i++) {
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gpio_set_mode(ptr[i].gpio, ptr[i].func);
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if (bus <= I2C4)
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gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP);
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}
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}
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static int mtk_i2c_max_step_cnt(uint32_t target_speed)
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{
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if (target_speed > I2C_SPEED_FAST_PLUS)
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return MAX_HS_STEP_CNT_DIV;
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else
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return MAX_STEP_CNT_DIV;
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}
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/*
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* Check and calculate i2c ac-timing.
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*
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* Hardware design:
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* sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
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* xxx_cnt_div = spec->min_xxx_ns / sample_ns
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*
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* The calculation of sample_ns is rounded down;
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* otherwise xxx_cnt_div would be greater than the smallest spec.
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* The sda_timing is chosen as the middle value between
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* the largest and smallest.
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*/
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static int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src,
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uint32_t check_speed,
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uint32_t step_cnt,
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uint32_t sample_cnt)
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{
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const struct i2c_spec_values *spec;
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uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
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uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100;
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uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src;
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struct mtk_i2c_ac_timing *ac_timing;
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spec = mtk_i2c_get_spec(check_speed);
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clk_ns = NSECS_PER_SEC / clk_src;
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su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
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if (su_sta_cnt > max_sta_cnt)
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return -1;
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low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
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max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
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if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) {
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if (low_cnt > step_cnt) {
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high_cnt = 2 * step_cnt - low_cnt;
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} else {
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high_cnt = step_cnt;
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low_cnt = step_cnt;
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}
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} else {
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return -2;
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}
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sda_max = spec->max_hd_dat_ns / sample_ns;
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if (sda_max > low_cnt)
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sda_max = 0;
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sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
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if (sda_min < low_cnt)
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sda_min = 0;
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if (sda_min > sda_max)
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return -3;
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ac_timing = &mtk_i2c_bus_controller[bus].ac_timing;
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if (check_speed > I2C_SPEED_FAST_PLUS) {
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ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8);
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ac_timing->ltiming &= ~GENMASK(15, 9);
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ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9);
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ac_timing->ext &= ~GENMASK(7, 1);
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ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0);
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} else {
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ac_timing->htiming = (sample_cnt << 8) | (high_cnt);
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ac_timing->ltiming = (sample_cnt << 6) | (low_cnt);
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ac_timing->ext = (su_sta_cnt << 8) | (1 << 0);
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}
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return 0;
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}
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/*
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* Calculate i2c port speed.
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*
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* Hardware design:
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* i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
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* clock_div: fixed in hardware, but may be various in different SoCs
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*
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* To calculate sample_cnt and step_cnt, we pick the highest bus frequency
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* that is still no larger than i2c->speed_hz.
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*/
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static int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
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uint32_t target_speed,
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uint32_t *timing_step_cnt,
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uint32_t *timing_sample_cnt)
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{
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uint32_t step_cnt;
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uint32_t sample_cnt;
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uint32_t max_step_cnt;
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uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV;
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uint32_t base_step_cnt;
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uint32_t opt_div;
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uint32_t best_mul;
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uint32_t cnt_mul;
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uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div;
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int32_t clock_div_constraint = 0;
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int success = 0;
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if (target_speed > I2C_SPEED_HIGH)
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target_speed = I2C_SPEED_HIGH;
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max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
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base_step_cnt = max_step_cnt;
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/* Find the best combination */
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opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
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best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
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/* Search for the best pair (sample_cnt, step_cnt) with
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* 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
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* 0 < step_cnt < max_step_cnt
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* sample_cnt * step_cnt >= opt_div
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* optimizing for sample_cnt * step_cnt being minimal
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*/
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for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
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if (sample_cnt == 1) {
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if (clk_div != 0)
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clock_div_constraint = 1;
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else
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clock_div_constraint = 0;
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} else {
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if (clk_div > 1)
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clock_div_constraint = 1;
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else if (clk_div == 0)
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clock_div_constraint = -1;
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else
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clock_div_constraint = 0;
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}
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step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt);
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if (step_cnt > max_step_cnt)
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continue;
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cnt_mul = step_cnt * sample_cnt;
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if (cnt_mul >= best_mul)
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continue;
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if (mtk_i2c_check_ac_timing(bus, clk_src,
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target_speed, step_cnt - 1,
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sample_cnt - 1))
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continue;
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success = 1;
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best_mul = cnt_mul;
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base_sample_cnt = sample_cnt;
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base_step_cnt = step_cnt;
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if (best_mul == opt_div + clock_div_constraint)
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break;
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}
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if (!success)
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return -1;
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sample_cnt = base_sample_cnt;
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step_cnt = base_step_cnt;
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if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) >
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target_speed)
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return -1;
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*timing_step_cnt = step_cnt - 1;
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*timing_sample_cnt = sample_cnt - 1;
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return 0;
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}
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static void mtk_i2c_speed_init(uint8_t bus, uint32_t speed)
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{
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uint32_t max_clk_div = MAX_CLOCK_DIV;
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uint32_t clk_src, clk_div, step_cnt, sample_cnt;
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uint32_t l_step_cnt, l_sample_cnt;
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uint32_t timing_reg_value, ltiming_reg_value;
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struct mtk_i2c *bus_ctrl;
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if (bus >= I2C_BUS_NUMBER) {
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printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus);
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return;
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}
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bus_ctrl = &mtk_i2c_bus_controller[bus];
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for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
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clk_src = I2C_CLK_HZ / clk_div;
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bus_ctrl->ac_timing.inter_clk_div = clk_div - 1;
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if (speed > I2C_SPEED_FAST_PLUS) {
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/* Set master code speed register */
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if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST,
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&l_step_cnt, &l_sample_cnt))
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continue;
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timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
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/* Set the high speed mode register */
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if (mtk_i2c_calculate_speed(bus, clk_src, speed,
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&step_cnt, &sample_cnt))
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continue;
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ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt |
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(sample_cnt << 12) | (step_cnt << 9);
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bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1);
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} else {
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if (mtk_i2c_calculate_speed(bus, clk_src, speed,
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&l_step_cnt, &l_sample_cnt))
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continue;
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timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
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/* Disable the high speed transaction */
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bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE;
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ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt;
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}
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break;
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}
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if (clk_div > max_clk_div) {
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printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus);
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return;
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}
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/* Init i2c bus timing register */
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write32(&bus_ctrl->i2c_regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
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write32(&bus_ctrl->i2c_regs->timing, bus_ctrl->ac_timing.htiming);
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write32(&bus_ctrl->i2c_regs->ltiming, bus_ctrl->ac_timing.ltiming);
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write32(&bus_ctrl->i2c_regs->hs, bus_ctrl->ac_timing.hs);
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write32(&bus_ctrl->i2c_regs->ext_conf, bus_ctrl->ac_timing.ext);
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}
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void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
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{
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mtk_i2c_speed_init(bus, speed);
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mtk_i2c_set_gpio_pinmux(bus);
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}
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void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
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{
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printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n",
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read32(®s->ltiming),
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read32(®s->clock_div));
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}
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