f4fa1e1d06
Add `decode_pcie_bar` for consistency with other Intel northbridges. Change-Id: If04ca3467bb067b28605a3acccb8bda325735999 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
171 lines
4.7 KiB
C
171 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
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#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
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/* Chipset types */
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#define HASWELL_MOBILE 0
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#define HASWELL_DESKTOP 1
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#define HASWELL_SERVER 2
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/* Intel Enhanced Debug region */
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#define IED_SIZE CONFIG_IED_REGION_SIZE
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/* Northbridge BARs */
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#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
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#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
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#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
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#define GFXVT_BASE_ADDRESS 0xfed90000ULL
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#define GFXVT_BASE_SIZE 0x1000
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#define VTVC0_BASE_ADDRESS 0xfed91000ULL
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#define VTVC0_BASE_SIZE 0x1000
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#include <southbridge/intel/lynxpoint/pch.h>
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/* Everything below this line is ignored in the DSDT */
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#ifndef __ACPI__
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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#include "hostbridge_regs.h"
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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#define MSAC 0x62 /* Multi Size Aperture Control */
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/*
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* MCHBAR
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*/
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#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
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#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
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#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
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#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
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#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
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#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or))
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#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
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#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
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#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
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/* As there are many registers, define them on a separate file */
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#include "mchbar_regs.h"
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#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
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#define DMAR_LCKDN (1 << 31)
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#define SPCAPCTRL (1 << 25)
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#define L3HIT2PEND_DIS (1 << 20)
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#define PRSCAPDIS (1 << 2)
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#define GLBIOTLBINV (1 << 1)
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#define GLBCTXTINV (1 << 0)
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/*
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* EPBAR - Egress Port Root Complex Register Block
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*/
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#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
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#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
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#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
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#define EPPVCCAP1 0x004 /* 32bit */
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#define EPPVCCAP2 0x008 /* 32bit */
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#define EPVC0RCAP 0x010 /* 32bit */
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#define EPVC0RCTL 0x014 /* 32bit */
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#define EPVC0RSTS 0x01a /* 16bit */
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#define EPVC1RCAP 0x01c /* 32bit */
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#define EPVC1RCTL 0x020 /* 32bit */
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#define EPVC1RSTS 0x026 /* 16bit */
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#define EPVC1MTS 0x028 /* 32bit */
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#define EPVC1IST 0x038 /* 64bit */
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#define EPESD 0x044 /* 32bit */
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#define EPLE1D 0x050 /* 32bit */
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#define EPLE1A 0x058 /* 64bit */
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#define EPLE2D 0x060 /* 32bit */
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#define EPLE2A 0x068 /* 64bit */
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#define PORTARB 0x100 /* 256bit */
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/*
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* DMIBAR
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*/
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#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
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#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
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#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
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#define DMIVCECH 0x000 /* 32bit */
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#define DMIPVCCAP1 0x004 /* 32bit */
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#define DMIPVCCAP2 0x008 /* 32bit */
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#define DMIPVCCCTL 0x00c /* 16bit */
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#define DMIVC0RCAP 0x010 /* 32bit */
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#define DMIVC0RCTL0 0x014 /* 32bit */
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#define DMIVC0RSTS 0x01a /* 16bit */
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#define DMIVC1RCAP 0x01c /* 32bit */
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#define DMIVC1RCTL 0x020 /* 32bit */
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#define DMIVC1RSTS 0x026 /* 16bit */
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#define DMILE1D 0x050 /* 32bit */
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#define DMILE1A 0x058 /* 64bit */
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#define DMILE2D 0x060 /* 32bit */
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#define DMILE2A 0x068 /* 64bit */
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#define DMILCAP 0x084 /* 32bit */
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#define DMILCTL 0x088 /* 16bit */
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#define DMILSTS 0x08a /* 16bit */
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#define DMILCTL2 0x098 /* 16bit */
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#define DMICTL1 0x0f0 /* 32bit */
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#define DMICTL2 0x0fc /* 32bit */
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#define DMIUESTS 0x1c4 /* 32bit */
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#define DMICESTS 0x1d0 /* 32bit */
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#define DMICC 0x208 /* 32bit */
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#define DMIL0SLAT 0x22c /* 32bit */
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#define DMILLTC 0x238 /* 32bit */
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#define DMI_AFE_PM_TMR 0xc28 /* 32bit */
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#define DMIDRCCFG 0xeb4 /* 32bit */
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#ifndef __ASSEMBLER__
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void intel_northbridge_haswell_finalize_smm(void);
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void mb_late_romstage_setup(void); /* optional */
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void haswell_early_initialization(void);
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void haswell_late_initialization(void);
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void set_translation_table(int start, int end, u64 base, int inc);
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void haswell_unhide_peg(void);
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void report_platform_info(void);
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int decode_pcie_bar(u32 *const base, u32 *const len);
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#include <device/device.h>
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struct acpi_rsdp;
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unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start,
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struct acpi_rsdp *rsdp);
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#endif /* __ASSEMBLER__ */
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#endif /* __ACPI__ */
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#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */
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