f4fe3c303c
The LPE audio device needs 1MiB of memory for its firmware.
It also has a requirement that the memory needs to be on a
512MiB boundary. Just take 1MiB @ 512MiB for the LPE device.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and analyzed console logs for resources. Also interrogated
registres within the kernel.
Change-Id: I4d9ad5c7b5a2f3eb627b30528d738289278b3a7b
Reviewed-on: https://chromium-review.googlesource.com/179192
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4994
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
122 lines
3.1 KiB
C
122 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <baytrail/iomap.h>
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#include <baytrail/pci_devs.h>
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#include <baytrail/pmc.h>
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#include <baytrail/ramstage.h>
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#include "chip.h"
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/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
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* address. Just take 1MiB @ 512MiB. */
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#define FIRMWARE_PHYS_BASE (512 << 20)
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#define FIRMWARE_PHYS_LENGTH (1 << 20)
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#define FIRMWARE_REG_BASE 0xa8
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#define FIRMWARE_REG_LENGTH 0xac
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static void setup_codec_clock(device_t dev)
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{
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uint32_t reg;
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int clk_reg;
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struct soc_intel_baytrail_config *config;
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const char *freq_str;
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config = dev->chip_info;
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switch (config->lpe_codec_clk_freq) {
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case 19:
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freq_str = "19.2";
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reg = CLK_FREQ_19P2MHZ;
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break;
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case 25:
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freq_str = "25";
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reg = CLK_FREQ_25MHZ;
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break;
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default:
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printk(BIOS_DEBUG, "LPE codec clock not required.\n");
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return;
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}
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/* Default to always running. */
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reg |= CLK_CTL_ON;
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if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) {
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printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n");
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return;
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}
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printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
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clk_reg = PMC_BASE_ADDRESS + PLT_CLK_CTL_0;
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clk_reg += 4 * config->lpe_codec_clk_num;
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write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
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}
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static void lpe_init(device_t dev)
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{
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setup_codec_clock(dev);
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}
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static void lpe_read_resources(device_t dev)
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{
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pci_dev_read_resources(dev);
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reserved_ram_resource(dev, FIRMWARE_REG_BASE,
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FIRMWARE_PHYS_BASE >> 10,
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FIRMWARE_PHYS_LENGTH >> 10);
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}
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static void lpe_set_resources(device_t dev)
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{
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struct resource *res;
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pci_dev_set_resources(dev);
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res = find_resource(dev, FIRMWARE_REG_BASE);
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if (res == NULL) {
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printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
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return;
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}
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pci_write_config32(dev, FIRMWARE_REG_BASE, res->base);
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pci_write_config32(dev, FIRMWARE_REG_LENGTH, res->size);
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}
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static const struct device_operations device_ops = {
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.read_resources = lpe_read_resources,
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.set_resources = lpe_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = lpe_init,
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.enable = NULL,
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.scan_bus = NULL,
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.ops_pci = &soc_pci_ops,
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};
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static const struct pci_driver southcluster __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = LPE_DEVID,
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};
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