Adds 64-bit (x86_64) support to libpayload's exception handler, previously limited to x86_32. Ensures `exception_init_asm` is called when building with LP_ARCH_X86_64 Kconfig. BUG=b:336265399 TEST=Successful build and boot of google/rex and google/rex64 on ChromeOS. Verified correct x86_64 exception handling by triggering "Debug Exception" using firmware-shell as below: firmware-shell: mm.l -0 Debug Exception Error code: n/a REG_IP: 0x0000000030023e9f REG_FLAGS: 0x0000000000000046 REG_AX: 0x0000000000000009 REG_BX: 0x0000000000000000 REG_CX: 0x0000002000000000 REG_DX: 0x0000000000000001 REG_SP: 0x0000000034072ec0 REG_BP: 0x0000000000000009 REG_SI: 0x0000000000000029 REG_DI: 0x0000000034072eef REG_R8: 0x0000000000000009 REG_R9: 0x0000000000000000 REG_R10: 0x0000000000000000 REG_R11: 0x0000000034072d70 REG_R12: 0x0000000000000004 REG_R13: 0x0000000000000001 REG_R14: 0x0000000034072ee6 REG_R15: 0x0000000000000004 CS: 0x0020 DS: 0x0000 ES: 0x0000 SS: 0x0018 FS: 0x0018 GS: 0x0050 Dumping stack: 0x340730c0: 3003c32e 00000000 ... 00000000 00000000 0x340730a0: 30034bc6 00000000 ... 0000002a 00000000 0x34073080: 34073234 00000000 ... 00002e65 00000000 ... ... 0x34072ee0: 340730ed 30300000 ... 34073000 00000000 0x34072ec0: 34072ed8 00000000 ... 00000000 00000008 Ready for GDB connection. Change-Id: I8f0aa1da8d179a760e8d49c3764dfd5a69d06887 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83036 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
		
			
				
	
	
		
			268 lines
		
	
	
		
			7.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			268 lines
		
	
	
		
			7.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 *
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 * Copyright 2013 Google Inc.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 * 3. The name of the author may not be used to endorse or promote products
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 *    derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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#include <arch/exception.h>
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#include <exception.h>
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#include <libpayload.h>
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#include <stdint.h>
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#include <arch/apic.h>
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#define IF_FLAG				(1 << 9)
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#if CONFIG(LP_ARCH_X86_64)
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#define REGISTER_FMT "0x%016zx"
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#else
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#define REGISTER_FMT "0x%08zx"
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#endif
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u8 exception_stack[0x400] __aligned(16);
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static interrupt_handler handlers[256];
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static const char *names[EXC_COUNT] = {
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	[EXC_DE]  = "Divide by Zero",
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	[EXC_DB]  = "Debug",
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	[EXC_NMI] = "Non-Maskable-Interrupt",
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	[EXC_BP]  = "Breakpoint",
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	[EXC_OF]  = "Overflow",
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	[EXC_BR]  = "Bound Range",
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	[EXC_UD]  = "Invalid Opcode",
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	[EXC_NM]  = "Device Not Available",
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	[EXC_DF]  = "Double Fault",
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	[EXC_TS]  = "Invalid TSS",
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	[EXC_NP]  = "Segment Not Present",
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	[EXC_SS]  = "Stack Fault",
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	[EXC_GP]  = "General Protection Fault",
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	[EXC_PF]  = "Page Fault",
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	[EXC_MF]  = "x87 Floating Point",
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	[EXC_AC]  = "Alignment Check",
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	[EXC_MC]  = "Machine Check",
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	[EXC_XF]  = "SIMD Floating Point",
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	[EXC_SX]  = "Security",
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};
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static void print_segment_error_code(u32 code)
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{
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	printf("%#x - descriptor %#x in the ", code, (code >> 3) & 0x1FFF);
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	if (code & (0x1 << 1)) {
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		printf("IDT");
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	} else {
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		if (code & 0x04)
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			printf("LDT");
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		else
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			printf("GDT");
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	}
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	if (code & (0x1 << 0))
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		printf(", external to the CPU");
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	else
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		printf(", internal to the CPU");
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}
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static void print_page_fault_error_code(u32 code)
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{
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	printf("%#x -", code);
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	if (code & (0x1 << 0))
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		printf(" page protection");
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	else
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		printf(" page not present");
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	if (code & (0x1 << 1))
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		printf(", write");
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	else
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		printf(", read");
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	if (code & (0x1 << 2))
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		printf(", user");
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	else
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		printf(", supervisor");
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	if (code & (0x1 << 3))
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		printf(", reserved bits set");
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	if (code & (0x1 << 4))
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		printf(", instruction fetch");
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}
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static void print_raw_error_code(u32 code)
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{
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	printf("%#x", code);
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}
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static void dump_stack(uintptr_t addr, size_t bytes)
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{
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	int i, j;
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	const int line = 8;
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	uint32_t *ptr = (uint32_t *)((uintptr_t)addr & ~(line * sizeof(*ptr) - 1));
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	printf("Dumping stack:\n");
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	for (i = bytes / sizeof(*ptr); i >= 0; i -= line) {
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		printf("%p: ", ptr + i);
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		for (j = i; j < i + line; j++) {
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			if ((uintptr_t)(ptr + j) >= addr && (uintptr_t)(ptr + j) < addr + bytes)
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				printf("%08x ", *(ptr + j));
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		}
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		printf("\n");
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	}
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}
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static void dump_exception_state(void)
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{
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	printf("%s Exception\n", names[exception_state->vector]);
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	printf("Error code: ");
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	switch (exception_state->vector) {
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	case EXC_PF:
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		print_page_fault_error_code(exception_state->error_code);
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		break;
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	case EXC_TS:
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	case EXC_NP:
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	case EXC_SS:
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	case EXC_GP:
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		print_segment_error_code(exception_state->error_code);
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		break;
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	case EXC_DF:
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	case EXC_AC:
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	case EXC_SX:
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		print_raw_error_code(exception_state->error_code);
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		break;
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	default:
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		printf("n/a");
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		break;
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	}
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	printf("\n");
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	printf("REG_IP:    " REGISTER_FMT "\n", exception_state->regs.reg_ip);
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	printf("REG_FLAGS: " REGISTER_FMT "\n", exception_state->regs.reg_flags);
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	printf("REG_AX:    " REGISTER_FMT "\n", exception_state->regs.reg_ax);
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	printf("REG_BX:    " REGISTER_FMT "\n", exception_state->regs.reg_bx);
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	printf("REG_CX:    " REGISTER_FMT "\n", exception_state->regs.reg_cx);
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	printf("REG_DX:    " REGISTER_FMT "\n", exception_state->regs.reg_dx);
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	printf("REG_SP:    " REGISTER_FMT "\n", exception_state->regs.reg_sp);
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	printf("REG_BP:    " REGISTER_FMT "\n", exception_state->regs.reg_bp);
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	printf("REG_SI:    " REGISTER_FMT "\n", exception_state->regs.reg_si);
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	printf("REG_DI:    " REGISTER_FMT "\n", exception_state->regs.reg_di);
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#if CONFIG(LP_ARCH_X86_64)
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	printf("REG_R8:    0x%016zx\n", exception_state->regs.reg_r8);
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	printf("REG_R9:    0x%016zx\n", exception_state->regs.reg_r9);
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	printf("REG_R10:   0x%016zx\n", exception_state->regs.reg_r10);
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	printf("REG_R11:   0x%016zx\n", exception_state->regs.reg_r11);
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	printf("REG_R12:   0x%016zx\n", exception_state->regs.reg_r12);
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	printf("REG_R13:   0x%016zx\n", exception_state->regs.reg_r13);
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	printf("REG_R14:   0x%016zx\n", exception_state->regs.reg_r14);
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	printf("REG_R15:   0x%016zx\n", exception_state->regs.reg_r15);
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#endif
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	printf("CS:     0x%04x\n", exception_state->regs.cs);
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	printf("DS:     0x%04x\n", exception_state->regs.ds);
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	printf("ES:     0x%04x\n", exception_state->regs.es);
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	printf("SS:     0x%04x\n", exception_state->regs.ss);
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	printf("FS:     0x%04x\n", exception_state->regs.fs);
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	printf("GS:     0x%04x\n", exception_state->regs.gs);
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}
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void exception_dispatch(void)
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{
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	die_if(exception_state->vector >= ARRAY_SIZE(handlers),
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	       "Invalid vector %zu\n", exception_state->vector);
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	u8 vec = exception_state->vector;
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	if (handlers[vec]) {
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		handlers[vec](vec);
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		goto success;
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	} else if (vec >= EXC_COUNT
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		   && CONFIG(LP_IGNORE_UNKNOWN_INTERRUPTS)) {
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		goto success;
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	} else if (vec >= EXC_COUNT
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		   && CONFIG(LP_LOG_UNKNOWN_INTERRUPTS)) {
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		printf("Ignoring interrupt vector %u\n", vec);
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		goto success;
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	}
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	die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u\n",
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	       vec);
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	dump_exception_state();
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	dump_stack(exception_state->regs.reg_sp, 512);
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	/* We don't call apic_eoi because we don't want to ack the interrupt and
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	   allow another interrupt to wake the processor. */
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	halt();
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	return;
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success:
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	if (CONFIG(LP_ENABLE_APIC))
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		apic_eoi(vec);
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}
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void exception_init(void)
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{
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	exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack);
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	exception_init_asm();
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}
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void set_interrupt_handler(u8 vector, interrupt_handler handler)
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{
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	handlers[vector] = handler;
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}
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#if CONFIG(LP_ARCH_X86_64)
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static uint64_t eflags(void)
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{
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	uint64_t eflags;
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	asm volatile(
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		"pushfq\n\t"
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		"popq %0\n\t"
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	: "=rm" (eflags));
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	return eflags;
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}
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#else
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static uint32_t eflags(void)
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{
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	uint32_t eflags;
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	asm volatile(
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		"pushf\n\t"
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		"pop %0\n\t"
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	: "=rm" (eflags));
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	return eflags;
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}
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#endif
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void enable_interrupts(void)
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{
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	asm volatile (
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		"sti\n"
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		: : : "cc"
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	);
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}
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void disable_interrupts(void)
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{
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	asm volatile (
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		"cli\n"
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		: : : "cc"
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	);
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}
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int interrupts_enabled(void)
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{
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	return !!(eflags() & IF_FLAG);
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}
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