f5627e8454
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I48422453735d50eb9292f39a3c031073d647a17c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <intelblocks/gpio.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/uart.h>
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#include <soc/iomap.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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const struct uart_gpio_pad_config uart_gpio_pads[] = {
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{
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.console_index = 0,
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.gpios = {
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
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},
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},
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{
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.console_index = 1,
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.gpios = {
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
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},
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},
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{
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.console_index = 2,
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.gpios = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
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},
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}
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};
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const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
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DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
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{
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/*
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* if index is valid, this function will return corresponding structure
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* for uart console else will return NULL.
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*/
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switch (uart_console) {
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case 0:
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return pcidev_path_on_root(PCH_DEVFN_UART0);
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case 1:
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return pcidev_path_on_root(PCH_DEVFN_UART1);
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case 2:
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return pcidev_path_on_root(PCH_DEVFN_UART2);
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default:
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printk(BIOS_ERR, "Invalid UART console index\n");
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return NULL;
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}
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}
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