f578b6f8f4
Done for consistency with other northbridges. Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
81 lines
2.2 KiB
C
81 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Use simple device model for this file even in ramstage */
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#define __SIMPLE_DEVICE__
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#include <arch/romstage.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <security/intel/txt/txt_platform.h>
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#include <security/intel/txt/txt_register.h>
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#include <types.h>
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#include "haswell.h"
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static uintptr_t northbridge_get_tseg_base(void)
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{
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return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB);
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}
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static uintptr_t northbridge_get_tseg_limit(void)
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{
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return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, BGSM), 1 * MiB);
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}
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union dpr_register txt_get_chipset_dpr(void)
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{
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return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) };
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}
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/*
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* Return the topmost memory address below 4 GiB available for general
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* use, from software's view of memory. Do not confuse this with TOLUD,
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* which applies to the DRAM as viewed by the memory controller itself.
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*/
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static uintptr_t top_of_low_usable_memory(void)
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{
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/*
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* Base of DPR is top of usable DRAM below 4 GiB. However, DPR
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* isn't always enabled. Unlike most memory map registers, the
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* DPR register stores top of DPR instead of its base address.
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* Unless binary-patched, Haswell MRC.bin does not enable DPR.
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* Top of DPR is R/O, and mirrored from TSEG base by hardware.
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*/
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uintptr_t tolum = northbridge_get_tseg_base();
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const union dpr_register dpr = txt_get_chipset_dpr();
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/* Subtract DMA Protected Range size if enabled */
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if (dpr.epm)
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tolum -= dpr.size * MiB;
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return tolum;
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}
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void *cbmem_top_chipset(void)
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{
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return (void *)top_of_low_usable_memory();
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_limit();
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*size -= *start;
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations.
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*/
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB);
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postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
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}
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